[rms:0.0.0.0:8885] [,] 2022-12-12 10:22:00.171 DEBUG 1040 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 10:22:00.218 DEBUG 1040 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 10:22:00.280 DEBUG 1040 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 10:22:00.312 DEBUG 1040 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:22:00.312 DEBUG 1040 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:22:00.327 DEBUG 1040 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 10:22:00.327 DEBUG 1040 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:22:00.327 DEBUG 1040 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:22:00.358 DEBUG 1040 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 10:22:00.364 DEBUG 1040 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:22:00.364 DEBUG 1040 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:22:00.428 DEBUG 1040 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 10:22:01.230 DEBUG 1040 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:22:01.232 DEBUG 1040 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:22:01.252 DEBUG 1040 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:22:01.254 DEBUG 1040 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:22:01.255 DEBUG 1040 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:22:01.273 DEBUG 1040 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:08.951 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:08.996 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:09.099 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:09.180 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:09.182 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:09.202 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:09.205 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:09.206 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:09.225 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:09.227 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:09.228 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:09.248 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:09.873 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:09.874 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:09.895 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:09.897 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:09.898 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:09.917 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:10.637 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:10.637 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:10.653 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 14
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:10.668 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:10.668 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 161(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:10.700 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 9
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:54.374 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:54.374 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:54.394 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:54.396 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:54.397 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:54.416 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:54.418 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:54.418 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:54.437 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:54.439 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:54.440 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:54.459 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:54.551 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND CREATE_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:54.551 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:54.570 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:54.603 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND CREATE_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:54.603 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:23:54.623 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:27.929 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:27.930 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:27.950 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:27.952 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:27.953 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:27.971 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:27.973 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:27.974 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:27.994 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:27.995 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:27.995 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.014 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.014 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.014 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.034 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.035 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.036 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.055 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.275 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.276 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.297 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 5
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.298 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.299 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 161(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.333 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.336 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.337 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 740226(Integer), 114(Integer), 0(Integer), 161(Integer), -1(Integer), 权要2(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.373 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.376 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.377 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 740227(Integer), 114(Integer), 0(Integer), 161(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.414 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.416 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.418 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 740228(Integer), 114(Integer), 0(Integer), 161(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.455 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.458 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.460 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 740229(Integer), 114(Integer), 0(Integer), 161(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.497 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.497 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.498 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 740230(Integer), 114(Integer), 0(Integer), 161(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.534 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.539 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.539 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 740231(Integer), 114(Integer), 0(Integer), 161(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.577 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.578 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.578 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 740232(Integer), 114(Integer), 0(Integer), 161(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.614 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.615 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.616 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 740233(Integer), 114(Integer), 0(Integer), 161(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.652 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.653 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.653 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 740234(Integer), 114(Integer), 0(Integer), 161(Integer), -1(Integer), 权要10(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:28:28.690 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:33:35.156 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:33:35.156 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 161(Integer), CN109924892B(String), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:33:35.188 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 14
[rms:0.0.0.0:8885] [,] 2022-12-12 10:33:35.207 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, EXPLAIN_TEXT, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:33:35.207 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 包括锅体、框体(String), 1.一种框式电饭煲,包括锅体、框体(String), 740225(Integer), 114(Integer), 0(Integer), 161(Integer), 1.一种框式电饭煲,包括锅体、框体(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:33:35.207 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 其特征在于(String), 其特征在于(String), 740225(Integer), 114(Integer), 0(Integer), 161(Integer), 其特征在于(String), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:33:35.207 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 740225(Integer), 114(Integer), 0(Integer), 161(Integer), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:33:35.207 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 顶部与承载部形成开放的锅体取放空间(String), 顶部与承载部形成开放的锅体取放空间(String), 740225(Integer), 114(Integer), 0(Integer), 161(Integer), 顶部与承载部形成开放的锅体取放空间(String), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:33:35.207 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 740226(Integer), 114(Integer), 0(Integer), 161(Integer), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:33:35.207 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 740227(Integer), 114(Integer), 0(Integer), 161(Integer), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:33:35.207 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 740228(Integer), 114(Integer), 0(Integer), 161(Integer), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:33:35.207 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 740229(Integer), 114(Integer), 0(Integer), 161(Integer), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:33:35.207 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 740230(Integer), 114(Integer), 0(Integer), 161(Integer), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:33:35.207 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 740231(Integer), 114(Integer), 0(Integer), 161(Integer), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:33:35.207 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 740232(Integer), 114(Integer), 0(Integer), 161(Integer), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:33:35.207 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 740233(Integer), 114(Integer), 0(Integer), 161(Integer), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:33:35.207 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 740234(Integer), 114(Integer), 0(Integer), 161(Integer), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:03.062 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:03.063 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:03.081 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:03.083 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:03.084 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:03.101 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:03.102 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:03.102 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:03.120 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:03.127 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:03.127 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:03.145 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:03.146 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:03.146 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:03.164 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:04.080 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:04.081 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 161(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:04.101 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:04.104 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:04.104 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:04.122 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:04.127 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:04.128 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:04.147 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:04.580 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:04.580 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:04.597 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:06.684 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM IMPORT_TASK WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:06.684 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==> Parameters: 161(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:06.700 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:21.269 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.insert ==>  Preparing: INSERT INTO IMPORT_TASK ( TASK_NAME, REPORT_ID, IMPORT_COUNT, CREATE_USER_ID, CREATE_USER_NAME, FILE_PATH, STATE, TYPE ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:21.269 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.insert ==> Parameters: CN109924892B及对比专利相关信息 - 副本.XLSX(String), 161(Integer), 9(Integer), 114(Integer), 朱鎏(String), \20221212\2f815c63bb794bec8c369f7ad99bdf51.XLSX(String), 0(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:21.300 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:21.337 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM IMPORT_TASK WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:21.337 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==> Parameters: 161(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:21.368 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:21.368 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectPage ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ? AND STATE = ?) ORDER BY CREATE_DATE DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:21.368 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectPage ==> Parameters: 161(Integer), 0(Integer), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:21.384 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:21.509 DEBUG 6676 [async-service-1] cn.cslg.report.mapper.ImportTaskMapper.updateById ==>  Preparing: UPDATE IMPORT_TASK SET TASK_NAME=?, REPORT_ID=?, IMPORT_COUNT=?, FINISH_TIME=?, CREATE_USER_ID=?, CREATE_USER_NAME=?, FILE_PATH=?, STATE=?, TYPE=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:21.509 DEBUG 6676 [async-service-1] cn.cslg.report.mapper.ImportTaskMapper.updateById ==> Parameters: CN109924892B及对比专利相关信息 - 副本.XLSX(String), 161(Integer), 9(Integer), 2022-12-12 10:37:21.0(Timestamp), 114(Integer), 朱鎏(String), \20221212\2f815c63bb794bec8c369f7ad99bdf51.XLSX(String), 1(Integer), 0(Integer), 85(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:37:21.540 DEBUG 6676 [async-service-1] cn.cslg.report.mapper.ImportTaskMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:38:51.885 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM IMPORT_TASK WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:38:51.885 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==> Parameters: 161(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:38:51.902 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:38:51.903 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectPage ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ? AND STATE = ?) ORDER BY CREATE_DATE DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:38:51.903 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectPage ==> Parameters: 161(Integer), 1(Integer), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:38:51.922 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:38:53.330 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM IMPORT_TASK WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:38:53.330 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==> Parameters: 161(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:38:53.348 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.822 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.823 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.840 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.842 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.842 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.857 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.858 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 161(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.858 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.859 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.859 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.876 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.877 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.877 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.878 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.878 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.878 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.896 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.896 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.896 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.897 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.897 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.897 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.913 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.914 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.914 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.914 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.914 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.915 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.933 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:33.934 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:34.171 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:34.171 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:34.188 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:34.482 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:34.482 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:34.814 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:34.815 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:34.815 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 161(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:34.850 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.344 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.344 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.360 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.361 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.363 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.364 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.364 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.378 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.379 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.380 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.381 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.382 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.382 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.397 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.398 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.399 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.400 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.400 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.401 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.417 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.417 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.418 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.418 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.434 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.434 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.435 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.435 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.435 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.453 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.461 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.461 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 161(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.504 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.504 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.520 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.727 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.728 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.728 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.746 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.941 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.942 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.977 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.978 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:37.978 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 161(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:38.000 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:38.233 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:38.237 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:38.237 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:38.254 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:38.254 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:38.255 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:42:38.273 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.453 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.453 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.469 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.469 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.469 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.469 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.469 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.486 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.486 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.486 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.486 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.486 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.486 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.502 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.502 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.502 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.502 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.502 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.502 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.518 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.518 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.518 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.518 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.537 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.537 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.537 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.537 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.537 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.553 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.553 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.553 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.569 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.569 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.569 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 161(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.569 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.587 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.587 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.587 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.607 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.607 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.607 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.607 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.607 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.622 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.622 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.768 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.768 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.801 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.815 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.815 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 161(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:11.847 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.894 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.894 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.910 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.910 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.910 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.910 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.910 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.925 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.925 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.925 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.925 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.925 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.925 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.941 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.941 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.941 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.941 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.941 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.941 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.957 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.957 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.957 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.957 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.980 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.980 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.980 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.980 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.980 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.980 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.980 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 161(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:29.988 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.004 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.005 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.005 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.006 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.006 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.007 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.022 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.023 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.023 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.024 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.042 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.055 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.055 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.072 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.215 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.215 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.241 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.243 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.243 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 161(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:30.288 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:38.134 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM IMPORT_TASK WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:38.134 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==> Parameters: 161(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:38.151 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:39.167 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM IMPORT_TASK WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:39.167 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==> Parameters: 161(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:39.184 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:39.184 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectPage ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ? AND STATE = ?) ORDER BY CREATE_DATE DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:39.185 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectPage ==> Parameters: 161(Integer), 1(Integer), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:39.202 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:42.251 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM IMPORT_TASK WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:42.252 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==> Parameters: 161(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:43:42.268 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:10.260 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND CREATE_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:10.261 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:10.264 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:10.264 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:10.278 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:10.282 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:10.283 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:10.284 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND CREATE_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:10.284 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:10.284 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:10.301 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:10.301 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:10.302 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:10.302 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:10.319 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:10.320 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:10.320 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:10.337 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:12.623 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:12.624 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:12.642 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:12.648 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:12.648 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:12.665 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:12.793 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM IMPORT_TASK WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:12.793 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==> Parameters: 161(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:12.811 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:12.811 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectPage ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ? AND STATE = ?) ORDER BY CREATE_DATE DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:12.811 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectPage ==> Parameters: 161(Integer), 1(Integer), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:12.830 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:13.664 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND CREATE_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:13.664 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:13.685 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:13.685 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND CREATE_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:13.685 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:13.706 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.026 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.026 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.043 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.044 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.044 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.061 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.061 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.062 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 161(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.062 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.063 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.080 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.080 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.081 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.081 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.081 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.081 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.099 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.099 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.099 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.099 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.099 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.099 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.109 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.110 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.116 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.116 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.127 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.128 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.128 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.145 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.164 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.164 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.182 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.346 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.347 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.365 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.366 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.366 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 161(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:19.401 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.893 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.893 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.909 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.909 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.909 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.909 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.909 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.924 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.924 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.924 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.924 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.924 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.924 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.940 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.956 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.956 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.956 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.956 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.956 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.971 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.971 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.971 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.971 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.987 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.987 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 161(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.987 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.987 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.987 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.987 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:21.987 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.007 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.007 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.008 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.008 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.008 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.008 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.008 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.025 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.025 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.026 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.026 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.044 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.056 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.056 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.073 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.216 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.216 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.250 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.252 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.252 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 161(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.286 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.686 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.687 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.703 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.705 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.705 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.722 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.722 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.722 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.740 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.784 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.785 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:44:22.801 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:02.357 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM IMPORT_TASK WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:02.357 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==> Parameters: 161(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:02.375 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:03.475 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM IMPORT_TASK WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:03.475 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==> Parameters: 161(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:03.492 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:03.492 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectPage ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ? AND STATE = ?) ORDER BY CREATE_DATE DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:03.492 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectPage ==> Parameters: 161(Integer), 1(Integer), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:03.509 DEBUG 6676 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:25.381 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:25.382 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:25.400 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:25.401 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:25.401 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:25.403 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM IMPORT_TASK WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:25.403 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==> Parameters: 161(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:25.418 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:25.419 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:25.419 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:25.422 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:25.436 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:25.437 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:25.437 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:25.454 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.591 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.592 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.609 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.610 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.610 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.628 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.630 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.630 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.631 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 161(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.631 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.649 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.649 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.649 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.666 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.667 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.669 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.669 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.669 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.669 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.688 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.688 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.690 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.691 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.707 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.707 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.709 DEBUG 6676 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.725 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.726 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.726 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.742 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.767 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.767 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.784 DEBUG 6676 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.967 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.967 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.985 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.985 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:26.986 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 161(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:27.020 DEBUG 6676 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.905 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.906 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.907 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.907 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.923 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.923 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.923 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.923 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.923 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.923 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.938 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.938 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.938 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.954 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.954 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.954 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.954 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.954 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.954 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.969 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.969 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.969 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.969 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.969 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.969 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 161(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.985 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.985 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.985 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.985 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.985 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.985 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.985 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:29.985 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:30.007 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:30.011 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:30.012 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:30.012 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:30.015 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:30.016 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:30.016 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:30.029 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:30.033 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:30.056 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:30.056 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:30.074 DEBUG 6676 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:30.221 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:30.221 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:30.239 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:30.240 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:30.240 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 161(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:47:30.273 DEBUG 6676 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.044 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.045 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.062 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.062 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.063 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.063 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.063 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.080 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.080 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.081 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.081 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.081 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.081 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.098 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.098 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.099 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.099 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.099 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.099 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.115 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.115 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 161(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.116 DEBUG 6676 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.116 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.117 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.117 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.134 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.135 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.135 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.136 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.136 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.136 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.137 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.137 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.154 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.154 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.154 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.155 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.155 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.155 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.156 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.171 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.172 DEBUG 6676 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.205 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.206 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.222 DEBUG 6676 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.373 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.373 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 161(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.391 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.391 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.391 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 161(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 10:48:24.425 DEBUG 6676 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:26.607 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:26.674 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:26.724 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:26.727 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND CREATE_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:26.728 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:26.748 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:26.749 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:26.750 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:26.770 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:26.772 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:26.772 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:26.780 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND CREATE_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:26.780 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:26.792 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:26.793 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:26.793 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:26.797 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:26.814 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:27.747 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:27.747 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:27.762 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:27.777 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:27.777 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:27.793 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:27.809 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:27.809 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 165(Integer), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:27.840 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:27.871 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:27.871 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:27.887 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.653 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.654 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.678 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.686 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.687 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.689 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.690 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.706 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.709 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.709 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.711 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.712 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.713 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.727 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.729 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.729 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.734 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.735 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.735 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 165(Integer), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.747 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.755 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.779 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.779 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:32.798 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:42.500 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:42.500 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:42.516 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:42.516 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:42.516 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:42.537 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:42.537 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:42.537 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:42.568 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:42.568 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:42.568 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:42.583 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:45.699 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:45.700 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:45.717 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:45.717 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:45.720 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:45.721 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:45.721 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:45.734 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:45.736 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:45.736 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:45.741 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:45.742 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:45.743 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:45.752 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:45.762 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:45.764 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:45.765 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:21:45.785 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.038 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.038 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.053 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.053 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.069 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.084 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.084 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.084 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.100 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.100 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.100 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.116 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.138 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.138 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.153 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.153 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.153 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.169 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.425 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.425 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.456 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 113
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.456 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.456 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.487 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.506 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.522 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.522 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.522 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.522 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.522 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.522 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.522 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.522 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.522 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.522 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.522 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.522 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.522 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.538 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.538 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.538 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.538 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.538 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.538 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.538 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.538 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.538 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.538 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.538 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:07.538 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.032 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.034 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.035 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.037 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.038 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.039 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.041 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.042 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.043 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.045 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.046 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.048 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.049 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.051 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.051 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.053 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.054 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.054 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.055 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.056 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.460 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.461 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.495 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.496 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.497 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.531 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.532 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.533 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.567 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.568 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.568 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.602 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.603 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.604 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.638 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.639 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.639 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.673 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.674 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.675 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.710 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.712 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.712 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.713 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.714 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.714 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.714 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.715 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.715 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.716 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.716 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.717 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.717 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.718 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.718 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.719 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.719 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.720 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.720 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.721 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.721 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.722 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.722 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.723 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.723 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.724 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:08.724 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.189 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.191 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.226 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.228 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.229 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.264 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.266 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.268 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.302 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.304 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.305 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.340 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.340 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.341 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.374 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.375 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.377 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.411 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.412 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.413 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.447 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.447 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.448 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.482 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.483 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.483 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.518 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.518 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.519 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.553 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.555 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.557 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.558 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.559 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.560 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.561 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.563 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.564 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.565 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.566 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.567 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.568 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.568 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.569 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.570 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.570 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.571 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.571 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.572 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.572 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.573 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.573 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.574 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.574 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.574 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:09.575 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.056 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.056 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.092 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.093 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.093 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.126 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.127 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.128 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.164 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.167 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.168 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.231 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.232 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.233 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.267 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.268 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.269 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.302 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.303 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.304 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.338 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.339 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.339 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.375 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.376 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.376 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.411 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.412 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.412 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.486 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.487 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.487 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.520 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.521 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.522 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.557 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.558 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.558 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.595 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.596 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.597 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.597 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.597 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.598 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.598 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.598 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.599 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.599 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.599 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.600 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.600 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.600 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.601 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.601 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.601 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.601 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.602 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.602 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.602 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.958 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.958 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.992 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.992 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:10.992 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.017 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.017 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.017 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.052 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.052 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.052 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.086 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.086 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.086 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.117 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.117 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.117 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.164 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.164 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.164 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.185 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.200 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.200 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.235 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.235 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.236 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.268 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.268 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.268 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.299 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.299 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.299 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.330 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.330 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.330 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:11.362 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.208 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.208 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.226 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.230 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.231 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.250 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.454 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.454 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.500 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 268
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.501 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.502 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.537 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.537 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.538 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.538 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.538 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.538 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.538 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.538 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.538 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.539 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.539 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.539 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.539 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.539 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.539 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.539 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.539 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.540 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.540 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.540 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.540 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.540 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.540 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.541 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.541 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.541 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.541 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.998 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.999 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.999 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.999 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.999 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.999 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:24.999 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.000 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.000 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.000 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.000 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.000 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.000 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.001 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.001 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.001 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.001 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.001 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.002 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.002 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.025 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.025 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.045 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.046 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.046 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.066 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.285 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.285 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.355 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.356 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.390 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.391 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.391 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.426 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.427 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.427 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.461 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.461 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.461 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.495 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.495 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.496 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.530 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.530 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.531 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.565 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.565 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.566 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.599 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.601 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.602 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.603 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.603 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.604 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.605 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.605 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.606 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.607 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.607 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.607 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.608 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.608 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.608 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.608 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.608 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.608 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.608 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.608 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.609 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.609 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.609 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.609 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.609 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.609 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.609 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.681 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 266
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.682 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.682 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.722 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.722 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.723 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.723 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.723 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.723 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.723 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.723 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.723 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.723 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.724 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.724 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.724 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.724 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.724 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.724 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.724 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.724 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.725 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.725 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.725 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.725 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.725 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.725 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.726 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.726 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:25.726 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.071 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.072 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.106 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.107 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.108 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.143 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.144 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.145 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.180 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.181 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.182 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.216 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.216 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.217 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.251 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.252 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.252 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.266 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.267 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.268 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.269 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.269 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.270 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.270 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.271 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.272 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.272 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.273 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.274 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.274 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.275 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.275 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.276 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.277 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.278 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.278 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.279 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.286 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.286 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.286 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.321 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.321 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.321 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.355 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.356 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.356 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.391 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.392 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.393 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.429 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.431 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.432 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.432 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.433 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.433 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.434 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.434 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.434 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.434 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.434 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.435 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.435 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.435 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.435 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.435 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.435 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.435 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.435 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.436 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.436 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.436 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.436 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.436 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.436 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.436 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.436 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.697 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.697 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.737 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.737 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.738 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.778 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.778 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.778 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.818 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.819 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.820 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.861 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.862 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.862 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.902 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.902 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.902 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.902 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.902 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.937 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.937 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.937 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.943 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.943 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.943 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.971 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.971 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.971 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.972 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.972 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.972 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.972 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.972 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.972 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.972 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.972 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.973 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.973 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.973 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.973 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.973 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.973 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.973 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.973 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.974 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.974 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.974 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.974 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.974 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.974 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.974 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.974 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.983 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.983 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:26.983 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.024 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.025 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.026 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.066 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.067 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.068 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.108 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.109 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.111 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.151 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.152 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.152 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.192 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.193 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.194 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.235 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.236 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.237 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.277 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.277 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.277 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.317 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.318 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.319 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.360 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.362 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.362 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.403 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.405 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.406 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.435 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.435 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.446 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.447 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.448 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.449 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.450 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.450 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.451 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.451 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.452 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.452 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.453 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.453 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.454 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.454 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.455 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.455 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.456 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.456 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.457 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.457 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.458 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.470 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.470 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.471 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.505 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.506 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.507 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.541 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.542 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.543 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.577 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.578 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.579 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.614 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.614 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.614 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.648 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.648 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.648 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.683 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.683 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.683 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.717 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.717 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.717 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.751 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.751 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.752 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.784 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.785 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.785 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.785 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.786 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.786 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.786 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.786 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.786 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.786 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.786 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.786 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.786 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.786 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.786 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.787 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.787 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.787 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.787 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.787 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.787 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.787 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.787 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.787 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.787 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.787 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.788 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.867 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.867 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.908 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.908 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.908 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.948 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.950 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.951 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.991 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.991 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:27.991 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.031 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.031 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.031 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.071 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.071 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.072 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.111 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.111 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.111 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.152 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.152 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.152 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.191 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.192 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.193 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.234 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.235 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.236 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.243 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.243 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.276 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.277 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.278 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.278 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.279 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.280 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.314 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.314 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.314 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.318 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.318 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.318 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.349 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.349 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.349 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.358 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.386 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.386 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.386 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.421 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.421 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.422 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.455 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.455 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.455 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.490 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.490 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.491 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.525 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.527 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.527 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.562 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.562 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.563 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.596 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.597 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.597 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.631 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.631 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.631 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.666 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.666 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.667 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.701 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.703 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.704 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.704 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.705 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.705 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.706 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.706 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.706 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.706 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.706 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.706 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.706 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.706 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.706 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.706 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.706 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.707 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.707 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.707 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:28.707 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.061 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.062 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.097 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.098 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.099 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.134 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.134 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.135 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.168 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.170 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.171 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.205 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.205 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.205 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.239 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.240 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.240 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.275 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.276 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.278 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.312 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.313 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.314 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.349 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.350 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.351 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.385 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.386 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.387 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.422 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.423 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.424 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.458 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.458 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.458 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:29.492 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.016 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.017 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.035 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.038 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.039 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.055 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.255 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.255 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.439 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 529
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.439 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.440 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.477 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 77
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.478 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.479 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.479 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.480 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.480 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.481 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.481 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.482 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.482 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.482 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.482 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.483 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.483 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.484 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.484 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.484 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.484 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.484 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.485 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.485 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.485 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.485 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.486 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.486 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.486 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.486 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.948 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.949 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.949 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.949 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.949 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.949 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.949 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.949 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.949 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.949 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.949 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.949 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.950 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.950 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.950 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.950 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.950 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.950 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.950 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:53.950 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.293 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.293 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.406 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.406 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.406 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.438 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.438 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.438 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.469 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.469 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.469 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.516 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.516 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.516 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.537 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.537 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.537 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.537 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:54.553 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.000 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.000 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.037 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.037 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.037 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.084 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.084 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.084 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.117 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.117 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.117 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.147 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.147 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.147 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.184 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.184 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.184 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.262 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.262 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.262 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.293 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.293 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.293 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.372 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.600 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.600 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.616 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.616 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.616 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.637 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.835 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.835 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.837 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.837 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.868 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.868 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.868 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.899 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.899 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.899 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.931 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.931 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.931 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.962 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.962 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.962 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.993 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.993 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:55.993 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.042 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.042 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.043 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.076 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.076 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.077 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.111 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.111 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.111 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.145 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.145 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.145 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.179 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.179 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.179 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.213 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.214 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.215 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.250 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.250 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.250 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.285 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.285 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.285 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.285 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.286 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.286 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.286 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.286 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.286 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.286 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.286 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.286 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.286 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.286 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.286 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.286 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.287 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.287 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.287 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.287 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.287 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.322 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 563
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.323 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.323 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.364 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 30
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.365 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.365 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.365 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.365 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.365 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.365 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.365 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.366 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.366 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.366 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.366 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.366 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.366 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.366 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.366 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.366 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.367 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.367 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.367 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.367 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.367 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.367 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.367 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.367 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.367 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.367 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.643 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.643 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.677 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.677 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.677 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.711 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.712 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.712 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.745 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.746 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.746 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.780 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.781 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.782 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.817 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.817 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.817 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.851 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.851 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.851 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.886 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.886 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.886 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.907 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.907 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.907 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.907 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.908 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.908 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.908 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.908 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.908 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.908 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.908 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.908 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.908 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.908 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.908 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.908 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.909 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.909 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.909 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.909 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.920 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.920 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.920 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.954 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.955 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.956 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.990 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.991 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:56.992 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.016 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.016 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.016 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.063 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.316 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.316 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.368 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.368 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.368 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.400 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.400 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.400 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.447 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.447 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.447 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.478 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.478 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.478 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.525 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.525 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.525 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.571 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.571 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.571 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:57.606 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.156 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.157 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.198 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.199 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.200 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.240 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.241 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.242 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.283 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.284 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.285 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.325 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.325 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.325 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.364 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.365 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.365 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.405 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.407 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.407 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.447 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.447 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.447 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.488 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.488 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.488 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.529 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.529 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.530 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.570 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.570 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.570 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.571 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.571 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.571 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.571 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.571 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.571 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.571 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.571 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.571 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.571 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.571 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.571 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.571 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.572 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.572 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.572 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.572 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.572 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.572 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.572 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.572 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.572 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.572 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:58.573 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.109 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.109 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.141 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.141 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.141 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.188 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.188 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.188 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.223 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.238 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.238 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.269 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.269 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.269 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.316 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.316 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.316 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.352 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.352 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.352 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.400 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.400 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.400 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.432 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.447 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.447 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.484 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.484 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.484 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.516 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.531 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.532 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.568 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.568 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.568 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.600 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.600 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.600 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:22:59.646 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.075 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.076 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.117 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.118 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.119 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.160 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.161 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.162 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.202 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.203 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.204 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.244 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.246 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.247 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.288 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.289 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.290 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.330 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.330 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.330 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.370 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.371 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.372 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.413 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.414 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.414 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.455 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.455 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.455 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.496 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.496 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.497 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.537 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.539 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.540 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:00.580 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:02.913 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:02.914 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:02.934 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:02.935 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:02.935 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:02.956 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:02.957 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:02.957 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:02.976 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:02.977 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:02.977 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:02.997 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:02.999 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:02.999 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.016 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.016 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.016 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.031 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.239 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.239 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.416 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 732
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.416 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.416 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.453 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 54
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:03.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.016 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.017 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.017 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.017 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.017 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.017 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.017 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.017 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.018 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.018 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.018 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.018 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.018 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.018 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.018 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.019 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.019 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.019 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.019 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.019 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.433 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.434 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.475 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.476 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.477 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.518 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.520 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.520 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.562 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.563 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.564 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.604 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.605 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.606 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.646 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.648 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.649 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.689 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.689 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.689 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.730 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.730 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.730 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.731 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.731 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.731 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.731 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.731 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.731 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.731 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.732 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.732 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.732 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.732 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.732 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.732 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.733 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.733 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.733 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.733 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.733 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.733 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.733 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.733 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.733 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.733 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:04.733 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.272 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.272 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.306 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.306 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.306 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.353 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.353 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.353 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.400 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.400 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.400 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.431 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.431 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.431 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.478 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.478 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.478 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.509 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.525 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.525 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.556 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.556 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.556 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.607 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.607 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.607 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.638 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.638 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.638 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.685 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:05.700 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.237 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.238 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.279 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.279 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.279 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.319 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.319 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.320 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.358 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.359 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.359 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.400 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.400 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.400 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.440 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.440 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.440 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.481 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.481 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.482 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.523 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.524 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.525 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.565 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.566 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.567 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.608 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.609 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.610 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.650 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.651 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.652 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.692 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.692 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.692 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.733 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.733 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.734 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.774 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.775 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.776 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.777 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.777 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.778 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.778 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.779 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.779 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.779 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.779 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.779 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.779 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.779 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.779 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.779 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.779 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.779 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.779 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.780 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:06.780 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.195 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.196 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.237 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.238 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.239 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.279 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.280 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.281 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.322 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.322 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.322 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.363 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.363 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.363 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.403 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.404 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.404 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.445 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.445 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.445 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.485 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.486 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.486 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.526 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.527 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.527 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.568 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.569 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.570 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.611 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.612 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.613 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.654 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.655 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.655 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:23:07.696 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:06.464 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:06.464 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:06.486 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:06.489 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:06.489 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:06.510 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:06.743 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:06.743 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.579 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 833
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.580 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.580 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.623 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.623 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.623 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.623 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.623 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.623 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.624 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.624 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.624 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.624 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.624 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.624 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.624 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.624 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.624 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.624 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.624 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.624 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.624 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.625 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.625 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.625 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.625 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.625 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.625 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.625 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:07.625 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.177 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.177 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.177 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.177 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.177 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.177 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.177 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.177 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.177 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.177 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.177 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.177 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.177 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.177 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.193 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.193 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.193 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.193 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.193 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.193 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.601 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.601 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.647 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.647 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.647 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.693 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.693 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.693 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.725 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.740 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.740 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.772 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.772 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.772 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.822 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.822 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.822 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.853 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.853 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.853 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:08.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.454 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.455 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.495 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.496 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.497 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.537 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.538 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.538 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.578 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.578 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.578 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.619 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.619 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.619 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.659 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.660 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.661 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.701 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.701 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.701 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.742 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.743 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.744 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.783 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.784 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.785 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.825 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.827 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.828 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.869 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.869 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.869 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.869 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.870 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.870 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.870 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.870 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.870 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.870 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.870 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.870 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.870 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.870 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.871 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.871 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.871 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.871 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.871 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.871 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.871 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.871 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.871 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.871 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.871 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.872 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.872 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.948 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.949 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.966 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.966 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.967 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:09.983 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.178 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.178 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.401 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.401 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.437 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.437 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.437 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.484 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.484 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.484 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.531 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.531 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.531 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.562 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.562 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.562 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.609 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.609 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.609 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.641 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.641 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.641 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.687 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.687 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.687 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.722 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.722 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.722 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.769 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.769 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.769 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.816 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.816 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.816 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.853 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.853 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.853 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.900 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:10.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.375 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.376 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.417 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.418 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.419 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.460 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.460 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.460 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.499 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.500 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.501 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.542 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.543 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.544 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.583 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.585 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.585 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.627 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.628 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.629 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.669 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.670 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.670 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.709 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.709 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.710 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.750 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.750 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.750 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.791 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.792 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.793 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.832 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.833 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.833 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.834 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 892
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.834 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.834 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.873 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.874 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.874 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.875 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.876 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.876 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.877 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.877 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.877 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.878 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.878 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.879 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.879 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.880 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.880 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.881 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.881 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.882 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.882 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.882 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.882 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.882 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.882 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.882 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.882 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.883 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.883 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:11.883 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.430 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.431 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.431 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.432 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.432 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.433 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.433 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.433 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.434 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.434 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.434 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.434 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.434 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.434 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.434 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.434 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.434 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.435 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.435 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.435 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.851 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.851 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.891 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.892 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.892 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.933 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.933 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.933 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.973 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.973 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:12.973 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.000 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.000 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.000 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.047 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.047 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.047 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.094 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.094 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.094 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.125 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.669 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.669 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.716 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.716 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.716 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.753 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.753 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.753 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.800 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.800 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.800 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.848 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.848 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.848 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.878 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.878 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.878 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.925 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.925 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.925 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.956 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.956 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:13.956 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.010 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.011 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.012 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.052 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.053 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.054 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.099 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.099 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.099 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.099 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.099 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.099 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.100 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.100 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.100 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.100 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.100 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.100 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.100 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.100 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.100 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.100 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.100 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.100 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.101 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.101 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.101 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.101 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.101 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.101 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.101 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.101 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.101 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.641 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.642 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.683 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.684 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.685 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.725 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.726 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.727 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.767 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.769 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.769 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.810 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.811 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.812 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.852 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.852 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.852 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.893 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.893 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.893 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.933 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.933 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.933 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.973 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.975 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:14.976 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.017 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.017 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.018 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.059 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.060 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.061 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.100 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.102 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.103 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.146 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.146 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.146 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.186 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.186 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.186 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.186 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.188 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.188 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.188 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.188 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.188 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.188 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.188 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.603 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.604 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.644 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.645 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.646 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.686 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.687 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.688 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.728 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.729 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.730 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.770 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.771 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.772 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.812 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.812 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.812 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.852 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.852 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.852 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.893 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.893 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.893 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.933 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.933 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.934 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.974 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.974 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:15.974 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:16.000 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:16.000 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:16.000 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:16.055 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:16.056 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:16.057 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:16.096 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:59.688 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:59.689 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:59.710 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:59.712 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:59.712 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:59.733 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:59.931 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:24:59.931 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.746 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1059
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.747 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.747 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.790 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.790 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.790 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.791 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.791 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.791 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.791 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.791 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.791 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.791 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.792 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.792 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.792 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.792 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.792 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.792 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.792 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.792 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.793 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.793 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.793 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.793 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.793 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.793 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.793 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.793 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:00.793 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.337 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.753 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.753 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.784 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.784 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.784 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.831 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.831 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.831 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.878 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.878 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.878 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.909 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.909 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.909 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.956 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.956 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:01.956 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.004 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.005 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.005 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.045 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.046 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.046 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.046 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.046 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.046 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.046 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.046 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.046 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.047 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.047 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.047 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.047 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.047 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.047 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.047 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.047 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.047 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.047 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.047 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.047 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.047 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.048 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.048 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.048 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.048 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.048 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.587 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.588 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.628 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.629 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.630 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.671 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.672 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.673 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.713 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.714 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.715 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.755 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.756 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.757 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.798 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.798 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.798 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.838 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.838 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.838 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.879 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.879 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.879 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.919 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.919 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.919 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.960 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.960 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:02.960 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.540 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.540 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.572 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.572 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.572 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.622 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.622 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.622 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.653 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.669 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.669 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.700 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.700 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.700 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.737 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.753 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.753 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.784 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.784 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.784 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.831 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.831 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.831 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.862 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.862 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.862 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.909 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.909 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.909 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.940 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.956 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.956 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.987 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.987 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:03.987 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.039 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.039 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.039 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.079 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.080 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.081 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.082 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.082 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.083 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.083 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.084 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.084 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.084 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.085 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.085 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.085 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.085 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.085 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.085 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.085 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.085 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.085 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.086 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.086 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.499 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.500 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.542 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.543 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.544 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.584 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.584 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.585 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.626 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.627 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.628 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.670 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.671 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.672 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.713 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.713 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.713 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.753 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.753 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.754 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.794 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.794 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.794 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.834 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.835 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.836 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.877 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.878 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.879 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.919 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.919 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.919 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.959 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.959 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:04.959 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:05.000 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:09.839 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:09.839 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:09.859 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:09.860 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:09.860 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:09.878 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:09.879 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:09.879 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:09.899 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:09.899 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:09.899 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:09.919 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:09.922 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:09.922 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:09.943 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:09.944 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:09.944 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:09.964 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:10.163 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:10.164 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.213 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1172
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.214 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.214 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.258 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.258 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.258 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.258 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.258 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.259 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.259 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.259 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.259 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.259 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.259 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.259 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.259 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.259 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.259 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.259 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.259 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.259 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.260 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.260 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.260 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.260 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.260 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.260 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.260 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.260 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.260 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.797 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.797 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.797 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.797 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.798 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.798 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.798 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.798 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.798 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.798 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.798 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.798 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.798 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.798 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.798 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.799 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.799 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.799 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.799 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:12.799 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.211 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.212 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.253 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.254 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.255 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.296 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.296 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.296 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.336 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.337 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.338 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.378 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.379 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.380 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.420 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.421 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.422 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.462 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.463 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.465 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.505 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.506 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.507 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.507 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.507 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.507 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.507 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.507 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.508 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.508 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.508 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.508 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.508 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.508 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.508 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.509 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.509 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.509 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.509 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.509 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.509 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.509 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.509 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.510 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.510 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.510 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:13.510 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.048 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.049 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.090 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.090 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.090 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.131 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.131 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.131 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.170 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.171 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.172 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.213 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.214 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.214 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.255 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.256 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.257 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.297 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.297 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.297 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.338 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.338 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.338 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.381 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.382 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.382 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.423 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.424 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.425 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.465 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.467 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.468 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.469 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.469 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.469 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.470 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.470 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.470 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.470 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.470 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.470 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.470 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.471 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.471 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.471 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.471 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.471 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.471 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.471 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.471 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.471 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.471 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.471 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.471 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:14.471 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.011 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.011 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.051 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.052 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.053 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.093 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.094 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.095 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.136 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.137 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.137 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.177 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.178 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.179 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.220 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.221 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.221 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.262 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.263 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.264 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.303 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.305 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.305 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.346 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.347 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.348 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.391 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.392 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.393 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.434 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.435 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.436 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.475 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.476 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.476 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.516 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.516 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.516 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.557 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.558 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.559 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.560 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.560 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.560 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.561 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.561 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.562 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.562 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.562 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.562 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.562 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.562 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.562 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.562 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.562 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.562 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.562 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.562 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.562 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.976 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:15.976 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.017 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.018 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.019 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.059 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.060 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.061 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.101 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.102 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.102 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.143 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.144 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.145 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.185 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.186 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.187 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.227 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.228 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.229 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.269 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.269 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.270 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.311 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.312 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.312 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.353 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.354 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.355 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.394 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.395 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.396 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.436 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.436 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.437 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:25:16.477 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:00.971 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:00.971 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:00.991 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:00.992 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:00.992 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:01.000 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:01.207 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:01.207 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.545 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.545 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.561 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.562 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.562 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.578 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.579 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.579 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.595 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.596 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.596 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.613 DEBUG 512 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.613 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.613 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.630 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.630 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.631 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.647 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.843 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:02.843 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.637 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1285
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.637 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.637 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:03.684 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.225 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.225 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.225 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.225 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.225 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.225 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.225 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.226 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.226 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.226 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.226 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.226 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.226 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.226 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.226 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.226 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.226 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.226 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.226 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.226 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.348 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1285
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.348 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.348 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.383 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.383 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.384 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.384 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.384 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.384 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.384 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.384 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.384 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.384 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.384 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.384 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.384 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.384 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.385 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.385 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.385 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.385 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.385 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.385 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.385 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.385 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.385 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.385 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.385 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.385 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.386 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.638 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.639 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.679 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.680 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.680 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.720 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.720 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.721 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.760 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.761 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.761 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.801 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.801 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.801 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.841 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.841 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.841 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.843 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.843 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.843 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.843 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.844 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.844 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.844 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.844 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.844 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.844 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.844 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.844 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.844 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.844 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.844 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.845 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.845 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.845 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.845 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.845 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.881 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.881 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.881 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.921 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.922 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.922 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.922 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.922 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.922 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.922 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.922 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.922 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.922 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.922 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.922 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.923 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.923 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.923 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.923 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.923 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.923 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.923 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.923 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.923 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.923 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.923 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.923 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.923 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.924 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:04.924 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.202 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.203 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.236 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.237 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.237 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.271 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.271 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.271 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.305 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.305 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.305 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.339 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.339 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.339 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.373 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.373 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.373 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.407 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.408 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.408 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.441 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.442 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.442 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.442 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.442 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.442 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.442 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.443 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.443 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.443 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.443 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.443 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.443 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.443 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.443 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.443 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.443 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.444 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.444 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.444 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.444 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.444 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.444 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.444 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.444 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.444 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.444 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.452 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.452 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.491 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.492 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.492 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.533 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.533 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.533 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.573 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.573 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.573 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.612 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.613 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.613 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.652 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.652 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.653 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.691 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.692 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.692 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.732 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.732 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.732 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.772 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.772 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.772 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.812 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.812 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.813 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.852 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.853 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.853 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.853 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.853 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.853 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.853 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.853 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.853 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.854 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.854 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.854 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.854 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.854 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.854 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.855 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.855 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.855 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.855 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.855 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.855 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.855 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.855 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.855 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.856 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.856 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.856 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.905 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.906 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.939 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.939 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.939 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.973 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.973 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:05.973 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.000 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.000 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.000 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.042 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.043 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.044 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.077 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.078 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.079 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.114 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.115 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.115 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.150 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.151 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.152 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.187 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.188 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.189 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.223 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.224 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.225 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.260 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.261 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.262 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.263 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.263 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.264 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.264 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.265 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.265 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.265 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.265 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.265 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.265 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.265 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.265 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.266 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.266 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.266 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.266 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.266 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.266 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.266 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.266 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.266 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.266 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.266 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.266 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.395 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.395 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.436 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.437 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.438 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.478 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.479 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.480 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.518 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.518 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.519 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.559 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.559 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.559 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.599 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.599 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.599 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.639 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.640 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.641 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.681 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.682 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.683 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.722 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.723 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.724 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.726 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.727 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.761 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.761 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.761 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.764 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.765 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.765 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.794 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.795 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.795 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.804 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.804 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.805 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.829 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.830 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.830 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.844 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.844 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.845 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.864 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.864 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.865 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.885 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.885 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.885 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.898 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.899 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.899 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.925 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.925 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.925 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.925 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.925 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.926 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.926 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.926 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.926 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.926 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.926 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.926 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.926 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.926 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.926 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.926 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.926 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.927 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.927 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.927 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.927 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.933 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.933 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.933 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.967 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.967 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:06.967 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.000 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.000 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.000 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.036 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.037 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.037 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.071 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.072 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.072 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.107 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.107 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.107 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.142 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.142 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.142 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.177 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.178 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.179 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.179 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.180 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.180 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.180 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.181 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.181 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.182 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.182 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.182 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.182 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.182 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.183 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.183 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.183 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.183 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.183 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.183 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.183 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.341 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.341 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.382 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.383 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.424 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.425 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.426 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.465 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.466 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.467 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.507 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.507 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.507 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.539 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.539 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.547 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.547 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.547 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.573 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.573 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.574 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.587 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.587 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.588 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.607 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.608 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.608 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.627 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.628 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.628 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.642 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.642 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.643 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.668 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.668 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.668 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.676 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.676 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.677 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.708 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.709 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.709 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.712 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.713 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.713 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.747 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.748 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.748 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.749 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.749 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.749 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.782 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.783 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.783 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.789 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.789 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.789 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.817 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.818 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.819 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.831 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.854 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.854 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.854 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.889 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.889 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.889 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.923 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.923 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.923 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:07.959 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.521 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.523 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.540 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.541 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.541 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.557 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.558 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.558 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.575 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.575 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.575 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.592 DEBUG 512 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.608 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.609 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.625 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.626 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.626 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.642 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.836 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:21.836 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.283 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1553
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.284 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.284 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.323 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 84
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.323 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.323 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.323 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.323 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.324 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.324 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.324 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.324 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.324 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.324 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.324 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.324 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.324 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.324 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.787 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.788 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.788 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.789 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.789 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.790 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.790 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.791 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.791 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.791 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.791 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.791 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.791 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.792 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.792 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.792 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.792 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.792 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.792 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:24.792 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.147 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.147 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.182 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.183 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.183 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.219 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.220 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.220 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.255 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.255 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.255 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.289 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.290 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.290 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.324 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.326 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.326 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.361 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.361 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.361 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.395 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.395 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.395 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.396 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.396 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.396 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.396 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.396 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.396 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.396 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.396 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.397 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.397 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.397 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.397 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.397 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.397 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.397 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.397 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.397 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.397 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.398 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.398 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.398 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.398 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.398 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.398 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.860 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.861 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.895 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.896 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.896 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.929 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.929 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.930 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.964 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.964 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:25.965 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.000 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.000 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.000 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.033 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.034 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.034 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.068 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.070 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.070 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.105 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.105 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.105 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.139 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.139 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.139 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.173 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.174 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.175 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.210 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.211 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.212 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.212 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.213 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.213 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.214 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.214 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.214 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.215 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.215 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.216 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.216 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.216 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.217 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.217 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.218 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.218 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.218 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.219 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.219 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.220 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.220 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.220 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.221 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.221 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.222 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.687 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.688 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.723 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.724 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.724 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.759 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.760 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.760 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.795 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.796 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.796 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.831 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.831 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.831 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.865 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.865 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.865 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.900 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.900 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.900 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.934 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.935 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.935 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.968 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.969 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:26.970 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.003 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.004 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.004 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.039 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.039 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.039 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.073 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.074 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.074 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.108 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.109 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.109 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.144 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.146 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.146 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.147 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.147 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.148 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.148 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.148 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.149 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.149 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.150 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.150 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.151 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.151 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.152 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.152 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.153 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.153 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.154 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.154 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.155 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.514 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.514 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.549 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.549 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.549 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.585 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.586 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.586 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.620 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.620 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.620 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.655 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.655 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.655 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.690 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.690 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.690 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.724 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.724 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.724 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.759 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.759 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.760 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.794 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.795 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.795 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.829 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.830 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.831 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.865 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.866 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.867 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.902 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.902 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.902 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:27.936 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.638 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.638 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.656 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.657 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.657 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.674 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.675 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.675 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.691 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.692 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.692 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.708 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.724 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.724 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.742 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.742 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.743 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.759 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.960 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:38.960 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.648 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1624
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.649 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.649 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.688 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.688 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.688 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.688 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.688 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.688 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.689 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.689 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.689 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.689 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.689 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.689 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.689 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.689 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.689 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.689 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.689 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.690 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.690 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.690 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.690 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.690 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.690 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.690 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.690 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.690 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:41.690 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.150 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.151 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.151 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.152 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.152 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.153 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.153 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.153 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.154 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.154 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.155 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.155 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.156 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.156 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.157 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.157 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.157 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.158 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.158 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.159 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.516 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.517 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.552 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.553 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.553 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.587 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.588 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.589 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.624 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.625 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.625 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.660 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.661 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.661 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.697 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.698 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.698 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.732 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.733 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.733 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.767 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.767 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.767 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.767 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.767 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.768 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.768 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.768 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.768 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.768 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.768 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.768 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.768 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.768 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.768 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.769 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.769 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.769 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.769 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.769 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.769 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.769 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.769 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.769 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.769 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.770 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:42.770 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.231 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.231 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.262 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.262 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.262 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.293 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.293 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.293 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.324 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.324 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.324 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.356 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.356 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.356 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.405 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.405 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.405 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.438 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.438 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.438 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.469 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.469 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.469 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.501 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.501 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.501 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.537 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.537 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.537 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.569 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:43.584 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.054 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.055 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.090 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.090 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.090 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.124 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.125 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.126 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.160 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.160 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.160 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.194 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.194 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.194 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.229 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.229 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.229 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.264 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.264 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.264 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.298 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.298 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.298 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.333 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.333 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.334 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.369 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.370 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.370 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.405 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.406 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.407 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.442 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.443 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.443 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.478 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.479 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.480 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.513 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.515 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.515 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.515 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.515 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.515 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.515 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.516 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.516 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.516 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.516 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.516 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.516 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.516 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.516 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.516 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.516 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.516 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.516 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.517 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.517 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.879 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.879 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.913 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.913 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.913 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.948 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.948 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.948 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.982 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.982 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:44.983 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.016 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.016 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.016 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.037 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.053 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.053 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.084 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.084 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.084 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.115 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.115 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.115 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.146 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.146 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.146 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.193 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.193 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.193 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.224 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.224 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.224 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.256 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.256 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.256 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:26:45.287 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:20.345 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:20.346 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:20.396 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:20.397 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:20.397 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:20.463 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:20.463 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:20.464 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:20.500 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:20.501 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:20.501 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:20.596 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:20.694 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:20.694 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:20.787 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:20.787 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:20.788 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:20.887 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:21.100 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:21.100 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:22.993 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1737
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:22.994 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:22.994 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.048 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.048 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.048 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.048 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.048 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.049 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.049 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.049 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.049 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.049 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.049 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.049 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.049 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.049 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.049 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.049 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.049 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.049 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.049 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.050 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.050 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.050 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.050 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.050 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.050 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.050 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:23.050 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.229 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.229 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.229 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.229 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.229 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.230 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.230 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.230 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.230 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.230 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.230 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.230 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.231 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.231 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.231 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.231 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.231 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.231 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.231 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.232 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.584 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.584 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.618 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.618 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.618 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.652 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.653 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.653 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.687 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.688 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.688 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.722 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.722 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.722 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.756 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.756 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.757 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.791 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.791 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.791 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.825 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.826 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.826 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.826 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.826 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.826 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.826 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.826 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.826 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.826 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.826 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.826 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.826 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.827 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.827 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.827 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.827 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.827 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.827 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.827 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.827 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.827 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.827 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.828 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.828 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.828 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:24.828 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.287 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.287 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.320 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.320 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.321 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.355 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.355 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.355 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.389 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.390 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.390 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.424 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.424 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.425 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.458 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.458 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.459 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.493 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.493 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.493 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.528 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.528 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.529 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.562 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.562 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.563 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.597 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.597 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.597 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.631 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.632 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.632 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.632 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.632 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.632 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.632 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.632 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.632 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.633 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.633 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.633 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.633 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.633 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.633 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.633 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.633 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.633 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.633 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.633 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.633 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.634 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.634 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.634 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.634 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.634 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:25.634 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.093 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.093 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.127 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.128 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.128 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.162 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.162 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.162 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.196 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.196 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.197 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.230 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.231 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.231 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.265 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.266 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.266 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.299 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.299 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.299 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.333 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.333 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.334 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.368 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.369 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.369 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.402 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.403 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.403 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.436 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.437 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.437 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.471 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.471 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.471 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.505 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.505 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.506 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.539 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.540 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.540 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.540 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.540 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.540 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.540 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.540 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.540 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.540 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.541 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.541 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.541 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.541 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.541 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.541 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.541 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.541 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.541 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.541 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.541 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.892 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.892 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.926 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.926 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.927 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.960 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.961 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.961 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.994 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.995 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:26.995 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.029 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.029 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.030 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.064 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.065 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.065 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.098 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.099 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.099 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.132 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.132 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.133 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.166 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.167 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.167 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.200 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.201 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.201 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.235 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.235 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.235 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.269 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.270 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.270 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:27.303 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.304 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.304 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.323 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.325 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.325 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.343 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.345 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.345 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.363 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.365 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.365 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.382 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.394 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.394 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.411 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.411 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.411 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.428 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.623 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:37.623 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.168 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1850
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.169 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.169 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.208 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.208 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.208 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.208 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.208 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.209 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.209 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.209 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.209 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.209 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.209 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.209 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.209 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.209 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.210 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.210 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.210 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.210 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.210 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.210 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.210 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.210 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.210 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.210 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.210 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.211 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.211 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.672 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.673 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.673 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.673 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.673 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.673 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.673 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.673 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.673 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.673 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.673 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.673 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.674 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.674 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.674 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.674 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.674 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.674 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.674 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:39.674 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.028 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.028 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.062 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.062 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.062 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.097 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.097 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.097 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.131 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.131 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.131 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.166 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.166 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.167 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.202 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.203 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.203 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.238 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.238 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.238 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.273 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.273 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.274 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.274 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.274 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.274 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.274 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.274 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.274 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.275 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.275 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.275 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.275 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.275 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.275 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.276 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.276 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.276 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.276 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.276 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.277 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.277 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.277 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.277 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.277 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.277 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.278 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.746 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.746 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.780 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.780 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.780 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.815 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.815 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.815 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.849 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.849 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.849 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.884 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.885 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.886 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.920 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.921 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.922 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.956 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.956 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.956 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.991 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.991 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:40.991 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.015 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.015 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.015 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.047 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.062 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.062 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.094 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.554 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.554 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.585 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.585 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.600 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.634 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.635 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.636 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.669 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.669 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.669 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.701 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.701 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.701 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.731 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.731 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.731 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.778 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.778 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.778 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.809 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.809 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.809 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.841 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.841 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.841 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.872 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.872 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.872 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.906 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.906 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.906 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.953 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.953 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.953 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.984 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.984 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:41.984 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.016 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.385 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.385 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.416 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.416 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.416 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.453 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.453 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.453 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.484 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.484 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.484 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.531 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.531 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.531 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.562 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.562 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.562 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.594 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.594 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.594 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.625 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.625 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.625 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.672 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.672 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.672 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.707 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.707 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.707 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.742 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.742 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.743 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.777 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.777 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.777 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:27:42.811 DEBUG 512 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:06.970 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:06.985 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:07.002 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:07.006 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:07.006 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:07.024 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:07.026 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:07.027 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:07.043 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:07.044 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:07.044 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:07.062 DEBUG 512 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:07.075 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:07.075 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:07.092 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:07.093 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:07.094 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:07.111 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:07.316 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:07.317 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.658 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1963
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.659 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.659 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.698 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.698 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.699 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.699 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.699 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.699 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.699 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.699 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.699 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.699 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.699 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.699 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.700 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.700 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.700 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.700 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.700 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.700 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.700 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.700 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.700 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.700 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.700 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.700 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.700 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.701 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:09.701 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.153 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.153 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.153 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.153 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.153 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.153 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.153 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.153 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.153 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.169 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.169 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.169 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.169 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.169 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.169 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.169 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.169 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.169 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.169 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.169 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.522 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.522 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.553 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.553 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.553 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.584 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.584 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.584 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.634 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.635 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.635 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.668 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.668 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.668 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.699 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.699 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.699 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.731 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.731 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.731 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.762 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.762 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.762 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.762 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.762 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.762 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.762 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.762 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.762 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.762 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.778 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.778 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.778 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.778 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.778 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.778 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.778 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.778 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.778 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.778 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.778 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.778 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.778 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.778 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.778 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.778 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:10.778 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.231 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.231 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.278 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.278 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.278 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.309 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.309 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.309 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.340 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.340 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.340 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.371 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.371 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.371 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.406 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.406 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.406 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.453 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.453 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.453 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.484 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.484 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.484 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.515 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.515 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.515 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.547 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.562 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.562 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:11.594 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.070 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.071 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.106 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.107 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.108 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.143 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.143 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.143 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.176 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.177 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.177 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.211 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.212 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.212 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.248 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.248 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.248 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.282 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.283 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.283 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.318 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.318 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.318 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.353 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.353 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.353 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.388 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.388 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.388 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.422 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.423 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.424 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.458 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.459 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.460 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.495 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.495 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.495 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.528 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.529 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.529 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.529 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.530 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.530 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.530 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.530 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.530 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.531 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.531 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.531 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.531 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.531 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.531 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.532 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.532 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.532 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.532 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.532 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.532 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.889 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.890 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.924 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.924 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.924 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.959 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.960 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.961 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.995 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.995 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:12.995 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.029 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.029 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.029 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.064 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.064 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.064 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.097 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.098 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.098 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.132 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.132 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.133 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.167 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.168 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.169 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.204 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.206 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.207 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.241 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.242 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.242 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.276 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.278 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.278 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:13.313 DEBUG 512 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:23.010 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:23.010 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:23.027 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:23.027 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:23.027 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:23.044 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:23.242 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:23.242 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.672 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 2076
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.672 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.672 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.706 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.706 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:25.722 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.186 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.186 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.186 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.186 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.186 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.187 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.188 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.188 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.543 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.544 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.579 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.580 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.581 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.615 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.616 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.617 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.651 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.652 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.653 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.688 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.689 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.690 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.724 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.725 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.726 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.760 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.760 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.760 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.795 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.795 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.795 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.796 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.796 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.796 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.796 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.796 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.796 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.796 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.796 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.797 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.797 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.797 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.797 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.797 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.797 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.797 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.797 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.798 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.798 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.798 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.798 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.798 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.798 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.798 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:26.798 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.259 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.259 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.293 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.293 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.293 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.327 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.328 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.329 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.363 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.364 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.364 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.399 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.400 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.401 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.436 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.437 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.438 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.472 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.472 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.472 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.507 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.507 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.507 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.542 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.542 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.542 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.576 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.577 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.578 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.613 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.614 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.615 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.615 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.616 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.616 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.617 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.617 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.617 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.618 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.618 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.618 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.618 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.618 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.618 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.618 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.618 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.618 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.618 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.618 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.618 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.619 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.619 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.619 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.619 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.619 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:27.619 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.080 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.082 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.115 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.115 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.115 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.147 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.147 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.147 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.178 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.178 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.178 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.225 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.225 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.225 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.256 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.256 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.256 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.287 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.287 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.287 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.322 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.322 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.322 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.354 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.354 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.354 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.385 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.385 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.385 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.434 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.435 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.436 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.469 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.469 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.469 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.500 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.500 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.500 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.537 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.906 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.906 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.938 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.938 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.938 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.970 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.970 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:28.970 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.011 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.012 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.013 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.047 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.048 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.049 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.083 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.084 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.085 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.120 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.121 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.122 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.156 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.156 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.156 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.191 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.191 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.191 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.225 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.225 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.225 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.260 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.261 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.262 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.296 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.297 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.298 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:28:29.332 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.352 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.352 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.369 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.369 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.370 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.386 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.387 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.387 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.402 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.403 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.403 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.420 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.438 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.439 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.459 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.459 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.459 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.480 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.704 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:34.704 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:37.978 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 2189
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:37.978 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:37.978 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.033 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.033 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.033 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.033 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.034 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.034 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.034 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.034 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.034 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.034 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.034 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.034 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.034 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.034 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.035 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.035 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.035 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.035 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.035 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.035 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.035 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.035 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.035 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.035 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.035 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.035 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.036 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.575 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.576 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.576 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.577 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.577 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.578 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.578 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.578 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.579 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.579 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.579 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.579 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.579 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.579 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.579 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.579 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.579 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.579 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.579 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.579 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.993 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:38.993 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.033 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.034 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.034 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.075 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.075 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.076 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.116 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.117 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.118 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.158 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.159 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.160 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.199 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.200 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.202 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.242 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.242 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.242 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.282 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.283 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.283 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.283 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.283 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.283 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.283 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.283 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.283 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.283 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.284 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.284 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.284 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.284 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.284 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.284 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.284 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.284 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.284 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.284 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.285 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.285 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.285 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.285 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.285 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.285 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.285 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.823 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.823 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.863 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.864 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.864 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.904 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.905 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.906 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.946 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.946 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.946 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.986 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.986 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:39.986 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.024 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.024 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.024 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.054 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.054 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.054 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.101 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.101 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.101 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.137 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.137 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.137 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.184 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.184 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.184 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.231 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.769 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.769 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.817 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.817 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.817 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.853 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.853 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.853 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.900 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.900 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.900 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.931 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.931 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.931 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.978 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.978 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:40.978 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.023 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.035 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.035 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.075 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.076 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.076 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.116 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.116 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.117 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.157 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.157 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.158 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.198 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.199 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.199 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.240 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.240 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.240 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.279 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.280 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.280 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.321 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.322 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.323 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.323 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.324 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.324 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.324 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.325 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.326 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.326 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.326 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.327 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.327 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.328 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.328 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.328 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.329 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.329 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.330 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.330 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.744 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.744 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.786 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.787 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.788 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.827 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.828 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.828 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.869 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.869 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.869 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.908 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.908 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.908 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.949 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.950 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.951 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.990 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.990 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:41.990 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:42.030 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:42.031 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:42.031 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:42.071 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:42.072 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:42.073 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:42.113 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:42.114 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:42.114 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:42.154 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:42.155 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:42.156 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:42.196 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:42.197 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:42.197 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:29:42.238 DEBUG 512 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.147 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.148 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.168 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.168 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.169 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.188 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.188 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.188 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.208 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.209 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.209 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.229 DEBUG 512 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.233 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.233 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.253 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.253 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.253 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.273 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.471 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:32.471 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.863 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 2302
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.864 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.864 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.910 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.910 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.910 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.910 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.911 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.911 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.911 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.911 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.911 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.911 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.911 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.911 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.911 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.911 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.911 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.911 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.911 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.912 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.912 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.912 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.912 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.912 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.912 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.912 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.912 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.912 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:35.912 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.452 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.452 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.453 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.453 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.454 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.454 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.455 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.455 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.455 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.456 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.456 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.456 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.456 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.456 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.456 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.456 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.456 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.456 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.456 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.456 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.871 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.871 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.911 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.912 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.912 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.952 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.952 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.952 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.992 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.992 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:36.992 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.032 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.033 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.033 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.073 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.073 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.073 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.113 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.115 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.115 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.156 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.156 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.156 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.156 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.156 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.156 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.157 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.157 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.157 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.157 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.157 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.157 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.157 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.157 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.157 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.157 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.157 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.157 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.157 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.158 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.158 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.158 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.158 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.158 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.158 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.158 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.158 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.693 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.693 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.733 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.734 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.734 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.775 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.775 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.775 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.815 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.816 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.816 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.856 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.857 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.858 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.898 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.899 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.899 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.940 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.940 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.940 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.979 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.980 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:37.980 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.020 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.020 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.020 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.061 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.061 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.061 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.101 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.102 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.102 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.103 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.103 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.104 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.104 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.104 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.105 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.105 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.105 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.106 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.106 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.107 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.107 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.107 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.108 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.108 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.108 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.109 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.110 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.110 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.110 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.111 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.111 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.111 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.112 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.649 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.649 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.690 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.691 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.692 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.732 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.733 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.734 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.775 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.775 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.775 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.816 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.816 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.816 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.856 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.856 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.856 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.897 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.897 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.897 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.937 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.937 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.937 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.977 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.977 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:38.977 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.017 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.018 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.018 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.058 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.058 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.058 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.098 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.098 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.098 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.138 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.138 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.138 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.178 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.179 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.180 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.181 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.181 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.181 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.182 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.182 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.183 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.183 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.183 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.184 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.184 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.185 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.185 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.185 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.186 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.186 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.186 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.187 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.187 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.602 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.603 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.643 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.644 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.644 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.685 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.686 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.687 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.727 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.728 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.728 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.769 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.770 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.771 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.810 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.810 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.810 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.851 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.851 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.852 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.892 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.893 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.894 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.934 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.934 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.934 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.975 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.975 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:39.976 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:40.000 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:40.016 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:40.016 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:40.056 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:40.056 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:40.056 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:30:40.095 DEBUG 512 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:48.565 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:48.565 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:48.584 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:48.585 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:48.585 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:48.605 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:48.818 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:48.818 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.852 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 2415
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.852 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.852 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.899 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.899 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.899 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.899 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.900 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.900 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.900 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.900 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.900 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.900 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.900 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.900 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.900 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.901 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.901 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.901 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.901 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.901 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.901 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.901 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.901 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.902 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.902 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.902 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.902 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.902 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:51.902 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.437 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.840 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.855 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.887 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.887 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.887 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.922 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.922 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.922 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.969 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.969 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:52.969 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.016 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.016 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.016 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.053 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.053 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.053 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.084 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.084 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.084 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.131 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.672 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.672 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.707 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.722 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.722 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.753 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.753 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.753 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.800 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.800 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.800 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.837 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.837 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.837 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.884 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.884 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.884 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.915 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.915 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.915 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.962 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.962 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:53.962 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.010 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.011 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.012 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.053 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.054 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.055 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.095 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.095 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.096 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.096 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.096 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.096 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.096 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.096 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.096 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.096 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.096 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.096 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.096 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.096 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.096 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.096 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.097 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.097 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.097 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.097 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.097 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.097 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.097 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.097 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.097 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.097 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.098 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.637 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.638 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.678 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.678 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.678 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.718 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.719 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.720 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.760 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.761 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.761 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.802 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.803 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.803 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.844 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.846 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.846 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.886 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.887 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.888 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.935 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.935 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.936 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.980 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.980 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:54.980 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.021 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.021 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.021 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.061 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.062 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.063 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.103 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.103 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.103 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.143 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.143 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.143 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.183 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.184 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.185 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.186 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.186 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.186 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.187 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.187 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.188 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.188 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.188 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.188 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.188 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.188 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.188 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.188 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.189 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.189 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.189 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.189 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.189 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.603 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.604 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.645 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.647 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.647 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.687 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.687 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.687 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.728 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.729 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.730 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.769 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.770 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.771 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.812 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.813 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.813 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.853 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.854 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.854 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.893 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.895 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.896 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.936 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.936 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.936 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.976 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.976 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:55.976 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:56.016 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:56.016 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:56.016 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:56.053 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:56.053 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:56.053 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:31:56.085 DEBUG 512 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:54.822 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:54.823 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:54.843 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:54.843 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:54.843 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:54.862 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:55.078 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:55.078 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.072 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 2528
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.073 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.073 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:36:59.654 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.078 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.078 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.118 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.119 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.119 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.159 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.160 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.160 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.200 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.200 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.200 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.241 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.241 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.241 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.281 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.281 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.281 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.322 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.322 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.322 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.362 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.362 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.362 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.362 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.362 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.363 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.363 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.363 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.363 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.363 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.363 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.363 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.363 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.363 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.363 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.364 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.364 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.364 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.364 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.364 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.364 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.364 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.364 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.364 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.364 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.364 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.364 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.903 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.903 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.943 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.943 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.943 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.986 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.986 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:00.986 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.026 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.027 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.028 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.068 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.069 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.069 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.109 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.109 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.109 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.151 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.151 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.151 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.192 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.193 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.194 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.234 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.235 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.236 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.277 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.279 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.279 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.320 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.321 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.322 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.322 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.323 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.323 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.324 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.324 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.324 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.325 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.325 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.325 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.325 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.325 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.325 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.325 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.325 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.325 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.325 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.325 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.325 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.325 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.326 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.326 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.326 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.326 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.326 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.864 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.865 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.905 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.906 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.906 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.946 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.986 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.986 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:01.986 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.016 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.016 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.016 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.069 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.069 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.069 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.100 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.100 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.100 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.147 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.147 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.147 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.178 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.194 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.194 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.225 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.225 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.225 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.272 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.272 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.272 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.306 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.306 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.306 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.353 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.353 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.353 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.384 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.801 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.801 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.837 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.837 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.837 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.884 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.884 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.884 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.931 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.931 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.931 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.962 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.962 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:02.962 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.014 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.014 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.015 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.054 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.054 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.054 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.094 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.094 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.094 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.135 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.135 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.136 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.175 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.176 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.176 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.216 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.216 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.216 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.256 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.257 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.258 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:37:03.299 DEBUG 512 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.584 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.599 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.631 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.646 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.646 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.662 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.662 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.662 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.682 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.697 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.697 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.713 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.729 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.729 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.744 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.744 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.744 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 163(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.937 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.937 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:42.953 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:45.222 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 2528
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:45.222 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:45.222 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:45.237 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:45.269 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:45.284 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 1.一种并联连接的谐振转换器电路(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 包含：多个谐振转换器(String), 以及输出电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 直流电源(String), 且提供输出电压Vo(String), 具正端与负端(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 输出电容(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 以及多个输入电容(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 每一输入电容具第一端与第二端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 且在动态情况下能够自动达到平衡点(String), 则停止(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 21.一种谐振转换器电路(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 第二谐振转换器(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 具两个输入端与两个输出端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 第二输入电容(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 则停止(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 21.一种谐振转换器电路(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 包含：第一谐振转换器(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 具两个输入端与两个输出端(String), 则停止(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 1.一种并联连接的谐振转换器电路(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 包含：多个谐振转换器(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 直流电源(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 具正端与负端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 输出电容(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 以及多个输入电容(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一输入电容具第一端与第二端(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 则停止(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 1.一种并联连接的谐振转换器电路(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含：多个谐振转换器(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 具正端与负端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 输出电容(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 以及多个输入电容(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 每一输入电容具第一端与第二端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 则停止(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 10.一种谐振转换器电路(String), 每一输入电容具第一端与第二端(String), 包含：至少第一与第二谐振转换器(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 第一输入电容(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 连接于所述第一谐振转换器的所述两个输入端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 且提供第一输入电压Vin1(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 第二输入电容(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 连接于所述第二谐振转换器的所述两个输入端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 且提供第二输入电压Vin2(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 以及输出电容(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 且提供输出电压Vo(String), 则停止(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 21.一种谐振转换器电路(String), 则停止(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 21.一种谐振转换器电路(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 包含：第一谐振转换器(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 具两个输入端与两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 则停止(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 35.一种谐振转换器电路(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 包含：第一谐振转换器(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 具两个输入端与两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 则停止(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:45.413 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:47.054 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM IMPORT_TASK WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:47.054 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==> Parameters: 163(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:47.069 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.507 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.507 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.525 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.527 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.527 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.545 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.719 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.719 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.739 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.740 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.741 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.753 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.754 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 163(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.758 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.759 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.761 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.976 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.977 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.997 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.998 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:49.998 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:50.019 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:50.021 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:50.021 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:50.042 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:50.086 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:50.086 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:50.107 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:56.266 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 2528
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:56.269 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:56.269 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:56.287 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:56.300 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:56.310 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 1.一种并联连接的谐振转换器电路(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 包含：多个谐振转换器(String), 以及输出电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 直流电源(String), 且提供输出电压Vo(String), 具正端与负端(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 输出电容(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 以及多个输入电容(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 每一输入电容具第一端与第二端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 且在动态情况下能够自动达到平衡点(String), 则停止(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 21.一种谐振转换器电路(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 第二谐振转换器(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 具两个输入端与两个输出端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 第二输入电容(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 则停止(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 21.一种谐振转换器电路(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 包含：第一谐振转换器(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 具两个输入端与两个输出端(String), 则停止(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 1.一种并联连接的谐振转换器电路(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 包含：多个谐振转换器(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 直流电源(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 具正端与负端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 输出电容(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 以及多个输入电容(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一输入电容具第一端与第二端(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 则停止(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 1.一种并联连接的谐振转换器电路(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含：多个谐振转换器(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 具正端与负端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 输出电容(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 以及多个输入电容(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 每一输入电容具第一端与第二端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 则停止(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 10.一种谐振转换器电路(String), 每一输入电容具第一端与第二端(String), 包含：至少第一与第二谐振转换器(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 第一输入电容(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 连接于所述第一谐振转换器的所述两个输入端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 且提供第一输入电压Vin1(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 第二输入电容(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 连接于所述第二谐振转换器的所述两个输入端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 且提供第二输入电压Vin2(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 以及输出电容(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 且提供输出电压Vo(String), 则停止(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 21.一种谐振转换器电路(String), 则停止(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 21.一种谐振转换器电路(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 包含：第一谐振转换器(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 具两个输入端与两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 则停止(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 35.一种谐振转换器电路(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 包含：第一谐振转换器(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 具两个输入端与两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 则停止(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:56.449 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.269 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 2641
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.269 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.269 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.307 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:57.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.218 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.219 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.255 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.256 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.256 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.293 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.294 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.294 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.331 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.332 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.333 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.371 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.373 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.374 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.412 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.412 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.413 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.449 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.450 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.451 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.487 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.488 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.488 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.489 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.489 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.489 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.489 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.489 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.490 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.490 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.490 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.490 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.490 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.491 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.491 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.491 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.491 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.491 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.491 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.492 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.492 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.492 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.492 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.492 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.493 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.493 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.493 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.986 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:58.987 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.016 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.016 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.016 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.047 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.062 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.062 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.094 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.094 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.094 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.125 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.125 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.125 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.172 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.172 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.172 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.207 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.207 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.207 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.239 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.239 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.254 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.285 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.285 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.285 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.324 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.324 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.324 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.369 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.369 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.369 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.369 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.369 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.369 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.369 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.369 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.369 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.369 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.369 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.369 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.369 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.369 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.369 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.369 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.369 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.854 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.854 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.902 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.903 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.903 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.938 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.938 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.938 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.969 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.969 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:40:59.969 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.000 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.016 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.016 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.053 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.053 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.053 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.084 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.084 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.084 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.115 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.115 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.115 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.162 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.162 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.162 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.198 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.198 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.198 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.229 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.229 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.229 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.276 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.276 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.276 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.307 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.307 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.307 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.731 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.731 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.762 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.778 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.778 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.814 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.814 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.814 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.845 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.845 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.845 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.883 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.883 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.883 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.929 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.929 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.929 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.961 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.961 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.961 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.997 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.997 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:00.997 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:01.042 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:01.042 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:01.043 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:01.078 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:01.079 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:01.079 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:01.116 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:01.116 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:01.117 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:01.153 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:01.153 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:01.154 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:01.190 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.411 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.411 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.428 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.431 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.432 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.450 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.458 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.458 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 166(Integer), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.476 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.502 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.502 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.520 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.682 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.683 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.711 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.713 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.714 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.731 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.732 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.733 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.750 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.751 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.752 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 11:41:11.769 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.565 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.565 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.586 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.588 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.589 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.608 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.609 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.609 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.628 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.630 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.630 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.649 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.654 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.654 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.673 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.673 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.673 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.692 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.692 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectPage ==>  Preparing: SELECT ID,CREATE_TIME,TASK_NAME,PROGRESS,TASK_STATUS,CREATE_ID,CREATE_NAME,BEGIN_TIME,FINISH_TIME,END_TIME,TYPE,REPORT_ID,HANDLE_PERSON_ID,HANDLE_PERSON_NAME,REMARK,RESULT,SIGN_PATENT_NO FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.692 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectPage ==> Parameters: 0(Integer), 154(Integer), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.711 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.711 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.712 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.731 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.731 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage ==>  Preparing: SELECT ID,CREATE_TIME,TASK_NAME,PROGRESS,TASK_STATUS,CREATE_ID,CREATE_NAME,BEGIN_TIME,FINISH_TIME,END_TIME,TYPE,REPORT_ID,HANDLE_PERSON_ID,HANDLE_PERSON_NAME,REMARK,RESULT,SIGN_PATENT_NO FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.732 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage ==> Parameters: 0(Integer), 154(Integer), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:16.752 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:17.632 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:17.633 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:17.652 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.238 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.238 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.248 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.249 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.257 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.266 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.267 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.267 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.282 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.282 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.285 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.285 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.285 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.301 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.301 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.301 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.303 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.319 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.320 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.320 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.339 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.340 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.340 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.359 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.360 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.360 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:20.379 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:22.151 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:22.151 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:22.168 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:22.187 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:22.187 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:22.205 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:22.206 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:22.206 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:22.223 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:22.224 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:22.224 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:22.242 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:32.339 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND CREATE_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:32.339 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:32.357 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:32.364 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND CREATE_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:32.364 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:32.381 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:33.893 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:33.893 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:33.912 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:33.917 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:33.918 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:33.935 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:33.936 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage ==>  Preparing: SELECT ID,CREATE_TIME,TASK_NAME,PROGRESS,TASK_STATUS,CREATE_ID,CREATE_NAME,BEGIN_TIME,FINISH_TIME,END_TIME,TYPE,REPORT_ID,HANDLE_PERSON_ID,HANDLE_PERSON_NAME,REMARK,RESULT,SIGN_PATENT_NO FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:33.936 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage ==> Parameters: 0(Integer), 154(Integer), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:06:33.954 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:26.901 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:26.901 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:26.918 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:26.918 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:26.918 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:26.935 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:26.936 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:26.936 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 166(Integer), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:26.952 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:26.979 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:26.979 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:26.996 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.765 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.765 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.765 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.765 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.783 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.783 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.783 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.783 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.783 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.783 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.799 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.799 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.799 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.799 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.799 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.799 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.822 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.823 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.832 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.833 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.833 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.833 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.833 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.833 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.856 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.857 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.857 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.858 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.877 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.878 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.878 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.898 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.904 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.904 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:33.924 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:34.046 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:34.046 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 163(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:34.122 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:34.122 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.293 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 2796
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.294 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.294 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.323 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.787 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.788 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.788 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.788 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.788 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.788 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.788 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.788 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.788 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.789 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.789 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.789 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.789 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.789 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.789 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.789 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.789 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.790 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.790 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.790 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.860 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 2641
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.861 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.862 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.883 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.896 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? 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[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:41.905 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 1.一种并联连接的谐振转换器电路(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 包含：多个谐振转换器(String), 以及输出电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 直流电源(String), 且提供输出电压Vo(String), 具正端与负端(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 输出电容(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 以及多个输入电容(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 每一输入电容具第一端与第二端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 且在动态情况下能够自动达到平衡点(String), 则停止(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 21.一种谐振转换器电路(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 第二谐振转换器(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 具两个输入端与两个输出端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 第二输入电容(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 则停止(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 21.一种谐振转换器电路(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 包含：第一谐振转换器(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 具两个输入端与两个输出端(String), 则停止(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 1.一种并联连接的谐振转换器电路(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 包含：多个谐振转换器(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 直流电源(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 具正端与负端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 输出电容(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 以及多个输入电容(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一输入电容具第一端与第二端(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 则停止(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 1.一种并联连接的谐振转换器电路(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含：多个谐振转换器(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 具正端与负端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 输出电容(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 以及多个输入电容(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 每一输入电容具第一端与第二端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 则停止(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 10.一种谐振转换器电路(String), 每一输入电容具第一端与第二端(String), 包含：至少第一与第二谐振转换器(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 第一输入电容(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 连接于所述第一谐振转换器的所述两个输入端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 且提供第一输入电压Vin1(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 第二输入电容(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 连接于所述第二谐振转换器的所述两个输入端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 且提供第二输入电压Vin2(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 以及输出电容(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 且提供输出电压Vo(String), 则停止(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 21.一种谐振转换器电路(String), 则停止(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 21.一种谐振转换器电路(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 包含：第一谐振转换器(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 具两个输入端与两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 则停止(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 35.一种谐振转换器电路(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 包含：第一谐振转换器(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 具两个输入端与两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 则停止(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.038 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.139 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.139 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.175 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.177 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.177 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.212 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.213 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.213 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.246 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.247 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.247 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.279 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.280 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.280 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.313 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.314 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.314 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.347 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.348 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.349 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.381 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.382 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.382 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.382 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.383 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.383 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.383 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.383 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.383 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.383 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.383 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.383 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.383 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.383 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.384 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.384 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.384 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.384 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.384 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.384 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.384 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.384 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.384 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.384 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.385 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.385 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.385 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.833 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.833 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.866 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.866 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.867 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.900 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.900 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.901 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.933 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.933 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.933 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.967 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.967 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:42.968 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.001 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.001 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.002 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.025 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.025 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.025 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.059 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.059 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.059 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.102 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.102 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.103 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.124 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.124 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.124 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.170 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.170 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.170 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.170 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.171 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.171 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.171 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.171 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.171 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.171 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.172 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.172 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.172 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.172 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.172 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.172 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.173 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.173 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.173 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.173 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.173 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.173 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.173 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.174 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.174 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.174 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.174 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.624 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.625 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.659 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.659 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.661 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.695 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.697 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.698 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.725 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.725 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.725 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.764 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.765 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.765 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.793 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.793 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.793 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.832 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.832 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.832 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.866 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.867 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.867 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.900 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.900 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.900 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.925 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.925 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.925 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.962 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.962 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:43.962 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.001 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.002 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.002 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.035 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.035 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.035 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.069 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.070 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.070 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.071 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.071 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.071 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.071 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.071 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.072 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.072 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.072 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.072 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.072 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.072 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.072 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.073 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.073 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.073 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.073 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.073 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.073 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.430 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.431 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.466 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.468 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.509 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.511 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.512 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.546 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.546 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.547 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.580 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.581 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.581 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.615 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.617 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.618 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.651 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.651 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.652 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.685 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.685 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.685 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.719 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.719 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.719 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.752 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.753 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.753 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.786 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.786 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.787 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.820 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.820 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.821 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:44.854 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:45.271 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:45.271 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:45.288 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:45.289 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:45.289 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:45.306 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:45.509 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:45.509 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.457 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 2909
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.458 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.458 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.498 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.498 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.499 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.499 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.499 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.499 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.499 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.499 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.500 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.500 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.500 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.500 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.500 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.500 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.500 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.500 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.501 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.501 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.501 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.501 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.501 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.501 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.501 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.501 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.501 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.501 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.501 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.954 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.955 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.956 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.956 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.957 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.957 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.958 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.958 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.958 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.958 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.958 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.958 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.958 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.958 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.959 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.959 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.959 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.959 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.959 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:49.959 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.308 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.308 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.342 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.342 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.343 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.376 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.376 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.377 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.410 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.411 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.411 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.444 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.445 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.445 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.478 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.480 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.481 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.516 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.516 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.517 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.550 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.550 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.551 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.551 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.551 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.551 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.551 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.551 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.551 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.551 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.552 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.552 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.552 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.552 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.552 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.552 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.552 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.552 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.552 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.552 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.553 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.553 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.553 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.553 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.553 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.553 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:50.553 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.002 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.004 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.037 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.039 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.040 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.074 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.074 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.074 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.107 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.108 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.108 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.143 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.144 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.145 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.178 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.179 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.180 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.214 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.214 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.214 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.247 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.247 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.247 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.281 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.281 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.282 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.316 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.316 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.316 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.349 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.351 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.352 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.353 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.353 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.354 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.354 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.354 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.354 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.355 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.355 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.355 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.355 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.355 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.355 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.355 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.355 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.355 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.355 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.355 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.356 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.356 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.356 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.356 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.356 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.356 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.356 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.804 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.804 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.838 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.838 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.838 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.872 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.872 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.872 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.905 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.906 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.906 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.938 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.939 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.939 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.973 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.973 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:51.973 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.007 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.007 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.007 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.040 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.040 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.040 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.074 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.074 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.075 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.107 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.107 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.108 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.141 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.141 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.141 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.168 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.168 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.168 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.211 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.211 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.212 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.244 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.245 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.245 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.245 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.245 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.245 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.245 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.245 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.246 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.246 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.246 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.246 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.246 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.246 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.246 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.246 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.246 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.246 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.247 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.247 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.247 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.585 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.585 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.625 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.625 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.626 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.659 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.661 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.661 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.686 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.686 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.686 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.730 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.730 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.731 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.765 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.767 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.767 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.800 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.800 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.800 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.835 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.838 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.839 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.869 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.869 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.869 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.903 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.903 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.903 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.940 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.940 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.940 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.973 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.974 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:52.974 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:26:53.007 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:13.264 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:13.264 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:13.280 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:13.281 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:13.281 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:13.297 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:13.597 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:13.598 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:14.936 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:14.937 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:14.956 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:14.957 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:14.957 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:14.977 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:14.978 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:14.978 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:14.997 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:14.998 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:14.998 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:15.007 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:15.023 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:15.023 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:15.044 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:15.044 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:15.045 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:15.065 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:16.274 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:16.274 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.028 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 3022
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.029 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.029 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.069 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.069 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.069 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.070 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.070 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.070 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.070 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.070 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.070 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.070 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.070 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.070 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.070 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.071 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.071 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.071 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.071 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.071 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.071 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.071 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.071 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.071 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.071 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.071 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.071 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.072 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.072 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.567 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.568 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.568 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.569 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.569 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.570 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.570 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.570 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.570 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.570 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.570 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.570 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.571 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.571 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.571 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.571 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.571 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.571 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.572 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.572 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.931 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.932 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.965 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.967 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:20.967 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.001 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.003 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.004 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.037 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.039 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.040 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.074 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.074 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.074 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.108 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.108 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.108 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.141 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.141 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.141 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.175 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.177 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.179 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.180 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.181 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.182 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.182 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.183 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.183 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.183 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.183 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.183 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.183 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.184 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.184 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.184 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.184 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.184 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.184 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.184 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.184 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.184 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.184 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.184 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.185 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.185 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.185 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.652 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.653 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.686 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.686 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.687 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.720 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.720 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.720 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.753 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.755 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.756 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.790 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.790 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.790 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.823 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.824 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.824 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.857 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.858 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.858 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.890 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.891 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.891 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.924 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.925 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.925 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.958 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.958 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.958 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.992 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.992 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.993 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.993 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.993 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.993 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.993 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.993 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.993 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.993 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.993 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.993 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.993 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.993 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.994 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.994 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.994 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.994 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.994 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.994 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.994 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.994 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.994 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.994 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.994 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.994 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:21.995 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.431 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.431 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.478 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.479 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.480 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.514 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.515 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.515 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.550 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.551 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.552 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.584 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.585 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.585 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.618 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.618 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.619 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.647 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.647 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.647 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.686 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.687 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.687 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.715 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.715 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.715 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.754 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.755 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.756 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.790 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.790 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.791 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.824 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.824 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.824 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.858 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.858 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.859 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:22.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.236 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.237 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.269 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.269 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.270 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.303 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.303 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.304 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.336 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.337 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.337 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.371 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.371 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.371 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.404 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.405 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.405 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.439 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.439 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.439 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.473 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.473 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.473 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.507 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.507 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.507 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.541 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.541 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.542 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.574 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.575 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.575 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.608 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.608 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.609 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.627 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 3022
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.628 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.628 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.642 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.676 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.676 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.677 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.677 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.677 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.677 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.677 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.677 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.677 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.677 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.678 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.678 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.678 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.678 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.678 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.678 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.678 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.678 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.678 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.678 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.678 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.679 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.679 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.679 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.679 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.679 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:23.679 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.228 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.228 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.228 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.228 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.228 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.228 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.228 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.229 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.229 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.229 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.229 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.229 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.229 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.229 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.229 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.229 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.229 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.229 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.230 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.230 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.655 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.656 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.698 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.700 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.701 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.743 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.743 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.743 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.784 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.784 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.785 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.826 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.826 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.826 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.867 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.868 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.868 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.909 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.910 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.911 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.951 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.951 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.952 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.952 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.952 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.952 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.952 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.952 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.952 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.952 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.952 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.952 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.953 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.953 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.953 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.953 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.953 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.953 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.953 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.954 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.954 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.954 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.954 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.954 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.954 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.954 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:24.954 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.502 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.502 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.549 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.551 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.551 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.586 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.586 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.586 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.635 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.636 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.636 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.678 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.680 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.680 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.718 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.718 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.718 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.763 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.763 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.764 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.805 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.805 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.806 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.846 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.846 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.847 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.884 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.884 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.884 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:25.923 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.481 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.482 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.522 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.522 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.523 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.552 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.552 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.552 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.602 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.602 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.602 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.647 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.647 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.647 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.684 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.684 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.684 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.730 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.731 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.731 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.772 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.772 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.773 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.802 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.802 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.802 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.854 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.854 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.854 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.885 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.885 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.885 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.937 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.937 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.938 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.978 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.978 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:26.978 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.020 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.021 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.021 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.021 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.021 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.021 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.022 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.022 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.022 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.022 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.022 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.022 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.022 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.022 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.022 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.022 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.022 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.023 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.023 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.023 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.023 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.446 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.446 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.491 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.492 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.493 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.535 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.535 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.535 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.590 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.590 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.590 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.633 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.633 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.634 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.675 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.676 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.676 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.717 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.719 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.720 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.761 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.761 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.761 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.805 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.805 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.805 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.846 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.846 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.847 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.894 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.895 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.895 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.943 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.943 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.943 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:27:27.983 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:16.752 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:16.753 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:16.774 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:16.777 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:16.778 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:16.799 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:17.153 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:17.153 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.232 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 3248
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.233 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.233 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.281 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.281 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.281 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.282 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.282 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.282 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.282 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.282 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.282 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.282 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.282 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.282 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.282 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.283 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.283 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.283 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.283 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.283 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.283 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.283 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.283 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.283 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.283 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.284 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.284 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.284 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.284 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.831 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.831 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.831 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.832 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.832 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.832 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.832 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.832 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.832 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.832 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.832 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.832 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.832 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.832 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.833 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.833 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.833 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.833 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.833 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:21.833 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.252 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.253 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.290 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.290 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.294 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.324 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.324 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.324 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.376 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.376 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.377 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.408 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.408 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.408 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.460 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.460 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.461 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.502 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.504 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.505 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.546 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.548 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.549 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.549 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.550 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.550 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.550 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.551 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.551 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.551 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.551 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.551 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.551 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.551 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.551 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.551 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.551 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.552 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.552 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.552 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.552 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.552 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.552 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.552 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.552 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.552 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:22.552 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.104 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.122 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.162 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.162 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.162 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.204 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.205 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.206 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.247 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.248 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.249 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.291 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.291 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.291 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.332 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.332 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.332 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.373 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.373 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.373 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.415 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.416 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.416 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.457 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.457 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.457 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.498 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.498 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.498 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.539 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.540 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.540 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.540 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.540 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.540 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.541 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.541 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.541 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.541 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.541 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.541 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.541 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.542 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.542 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.542 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.542 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.542 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.542 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.542 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.542 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.542 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.543 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.543 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.543 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.543 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:23.543 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.091 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.092 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.125 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.125 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.125 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.173 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.173 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.173 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.214 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.214 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.214 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.243 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.243 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.243 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.297 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.298 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.298 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.326 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.326 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.326 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.379 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.379 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.379 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.421 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.421 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.421 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.462 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.462 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.463 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.503 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.503 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.504 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.544 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.545 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.546 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.587 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.587 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.587 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.628 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.628 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.629 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.629 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.629 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.629 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.629 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.629 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.629 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.629 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.629 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.629 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.629 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.629 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.630 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.630 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.630 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.630 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.630 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.630 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:24.630 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.051 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.052 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.093 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.094 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.095 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.136 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.137 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.138 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.180 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.180 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.180 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.220 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.221 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.221 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.262 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.262 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.262 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.303 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.303 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.303 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.345 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.345 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.346 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.387 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.388 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.389 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.430 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.432 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.433 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.473 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.475 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.476 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.518 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.519 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.520 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:25.561 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:34.145 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:34.146 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:34.153 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:34.153 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:34.153 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:34.186 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:34.461 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:34.461 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.773 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 3361
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.773 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.773 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.821 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.821 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.822 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.822 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.822 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.822 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.822 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.822 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.822 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.822 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.822 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.822 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.822 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.822 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.823 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.823 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.823 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.823 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.823 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.823 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.823 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.823 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.823 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.823 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.823 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.823 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:38.824 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.380 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.380 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.381 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.381 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.381 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.381 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.381 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.382 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.382 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.382 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.382 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.382 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.382 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.382 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.382 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.382 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.382 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.382 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.382 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.383 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.802 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.803 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.843 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.843 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.843 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.885 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.885 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.886 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.927 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.929 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.931 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.972 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.974 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:39.975 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.016 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.016 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.016 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.057 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.057 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.057 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.098 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.098 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.099 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.099 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.099 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.099 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.099 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.099 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.099 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.099 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.099 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.099 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.099 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.099 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.100 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.100 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.100 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.100 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.100 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.100 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.100 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.100 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.100 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.100 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.100 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.100 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.101 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.648 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.648 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.689 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.689 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.689 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.731 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.731 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.732 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.774 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.774 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.774 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.816 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.816 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.816 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.857 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.857 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.858 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.899 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.899 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.899 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.941 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.942 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.942 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.982 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.982 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:40.982 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.025 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.026 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.026 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.047 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.047 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.063 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.064 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.064 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.068 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.068 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.068 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.068 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.068 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.069 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.069 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.069 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.069 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.069 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.069 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.069 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.069 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.069 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.069 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.069 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.069 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.069 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.070 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.070 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.070 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.070 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.070 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.070 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.070 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.070 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.070 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.079 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.080 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.080 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.097 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.098 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.098 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.114 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.114 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.114 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.130 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.130 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.131 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.147 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.402 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.402 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.619 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.620 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.660 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.660 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.661 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.702 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.702 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.702 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.744 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.744 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.745 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.785 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.786 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.786 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.827 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.828 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.828 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.869 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.869 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.869 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.910 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.911 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.911 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.953 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.953 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.953 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.994 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.995 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:41.995 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.036 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.038 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.038 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.079 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.080 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.080 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.121 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.121 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.121 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.162 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.164 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.164 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.164 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.164 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.164 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.164 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.164 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.164 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.164 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.165 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.165 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.165 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.165 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.165 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.165 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.165 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.165 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.165 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.165 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.165 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.587 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.588 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.630 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.630 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.630 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.672 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.672 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.672 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.713 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.713 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.713 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.755 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.755 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.755 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.795 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.796 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.796 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.837 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.838 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.838 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.878 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.881 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.881 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.921 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.923 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.924 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.961 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.961 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:42.961 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:43.007 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:43.008 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:43.008 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:43.049 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:43.049 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:43.049 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:43.090 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:44.513 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:44.513 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:44.536 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:44.536 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:44.537 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:44.556 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:45.948 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:45.949 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:45.971 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:45.974 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:45.974 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:45.994 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:45.994 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:45.995 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.015 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.015 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.016 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.036 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.039 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.039 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.059 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.060 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.060 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.068 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.068 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.147 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.953 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 3420
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.954 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.954 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.994 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.994 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.994 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.994 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.995 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.995 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.995 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.995 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.995 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.995 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.995 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.995 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.995 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.995 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.995 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.995 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.995 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.996 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.996 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.996 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.996 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.996 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.996 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.996 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.996 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.996 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:46.996 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.085 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.085 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.445 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.445 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.446 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.446 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.446 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.446 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.446 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.446 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.446 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.446 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.446 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.446 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.446 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.447 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.447 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.447 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.447 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.447 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.447 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.447 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.787 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.787 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.821 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.821 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.821 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.854 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.854 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.855 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.888 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.888 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.889 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.922 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.923 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.923 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.956 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.956 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.956 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.990 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.990 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:47.990 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.023 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.023 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.023 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.040 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.041 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.042 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.043 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.043 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.044 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.044 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.044 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.044 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.045 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.045 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.045 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.045 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.045 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.045 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.045 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.045 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.045 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.045 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.045 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.045 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.045 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.046 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.046 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.046 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.046 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.046 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.226 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.226 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.310 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.484 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.484 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.521 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.522 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.522 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.551 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.551 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.551 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.589 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.589 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.589 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.623 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.624 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.624 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.657 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.657 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.657 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.684 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.684 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.684 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.724 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.724 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.724 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.751 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.751 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.751 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.790 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.791 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.791 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.825 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.825 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.825 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.826 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.826 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.826 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.826 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.826 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.826 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.826 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.826 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.826 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.826 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.826 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.826 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.827 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.827 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.827 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.827 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.827 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.827 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.827 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.827 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.827 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.827 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.827 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:48.827 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.188 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.189 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.277 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.278 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.313 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.313 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.313 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.348 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.349 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.350 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.384 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.386 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.387 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.420 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.420 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.421 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.453 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.454 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.454 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.488 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.488 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.488 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.522 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.524 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.525 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.558 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.558 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.558 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.593 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.593 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.594 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.627 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.628 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.628 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.661 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.661 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.661 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.695 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.695 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.695 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.729 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.729 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.730 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.730 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.730 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.730 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.730 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.730 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.731 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.731 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.731 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.731 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.731 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.731 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.731 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.731 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.731 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.731 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.731 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.731 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:49.732 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.077 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.078 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.112 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.112 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.112 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.146 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.148 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.149 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.182 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.183 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.184 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.218 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.219 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.219 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.252 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.252 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.252 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.285 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.285 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.285 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.319 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.320 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.320 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.354 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.354 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.354 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.388 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.388 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.388 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.421 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.421 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.421 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.455 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.455 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.456 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:50.488 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:55.179 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:55.180 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:55.257 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:55.258 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:55.258 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:55.274 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:57.729 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:57.729 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:58.484 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:58.484 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:58.756 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:58.757 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:58.757 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:28:58.774 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.916 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 3437
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.916 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.917 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.965 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.965 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.965 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.965 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.966 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.966 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.966 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.966 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.966 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.966 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.966 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.966 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.966 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.966 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.966 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.966 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.967 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.967 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.967 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.967 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.967 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.967 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.967 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.967 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.967 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.967 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:01.967 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.516 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.516 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.517 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.517 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.517 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.517 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.517 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.517 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.517 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.517 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.517 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.517 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.517 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.517 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.517 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.518 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.518 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.518 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.518 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.518 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.939 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.939 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.980 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.982 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:02.983 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.024 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.025 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.025 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.066 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.067 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.067 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.107 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.107 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.107 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.149 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.149 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.150 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.190 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.190 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.191 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.232 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.233 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.233 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.234 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.234 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.234 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.234 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.234 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.234 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.234 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.234 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.234 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.234 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.234 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.235 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.235 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.235 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.235 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.235 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.235 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.235 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.235 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.235 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.235 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.235 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.235 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.236 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.544 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.544 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.788 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.788 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.827 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.829 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.829 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.869 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.869 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.870 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.911 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.911 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.911 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.949 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.949 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.949 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.983 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.983 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:03.983 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.036 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.036 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.036 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.077 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.078 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.078 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.119 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.120 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.120 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.161 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.163 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.164 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.204 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.206 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.207 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.208 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.208 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.208 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.209 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.209 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.210 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.210 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.211 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.211 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.211 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.212 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.212 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.213 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.213 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.213 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.214 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.214 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.215 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.215 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.215 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.216 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.217 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.217 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.217 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.808 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.808 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.849 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.850 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.851 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.891 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.892 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.892 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.932 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.933 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.933 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.975 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.975 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:04.975 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.006 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.017 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.017 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.058 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.058 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.058 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.098 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.101 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.102 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.143 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.143 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.143 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.183 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.186 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.187 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.228 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.229 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.230 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.270 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.272 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.273 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.314 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.314 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.314 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.355 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.355 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.355 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.355 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.356 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.356 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.356 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.356 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.356 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.356 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.356 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.356 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.356 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.356 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.356 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.356 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.357 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.357 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.357 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.357 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.357 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.767 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.783 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.784 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 3474
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.785 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.785 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.824 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.824 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.824 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.831 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 31
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.831 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.832 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.832 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.832 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.832 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.832 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.832 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.832 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.832 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.832 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.832 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.832 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.832 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.832 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.833 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.833 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.833 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.833 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.833 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.833 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.833 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.833 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.833 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.833 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.833 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.833 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.865 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.865 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.865 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.899 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.899 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.899 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.949 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.949 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.950 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.990 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.990 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:05.990 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.031 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.031 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.031 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.072 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.072 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.072 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.114 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.114 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.114 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.154 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.156 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.157 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.198 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.199 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.200 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.241 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.241 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.241 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.282 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.353 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.354 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.354 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.354 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.354 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.354 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.354 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.354 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.354 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.354 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.354 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.354 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.355 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.355 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.355 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.355 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.355 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.355 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.355 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.355 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.753 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.753 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.793 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.793 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.793 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.831 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.831 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.832 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.870 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.871 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.871 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.910 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.911 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.912 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.951 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.952 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.953 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.992 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.993 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:06.993 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.031 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.032 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.032 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.032 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.032 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.032 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.032 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.032 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.032 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.033 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.033 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.033 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.033 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.033 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.033 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.033 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.033 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.033 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.033 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.033 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.034 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.034 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.034 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.034 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.034 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.034 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.034 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.555 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.555 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.594 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.594 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.594 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.634 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.635 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.636 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.674 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.674 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.674 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.713 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.714 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.714 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.753 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.753 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.753 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.802 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.802 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.803 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.841 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.842 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.842 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.880 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.881 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.881 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.920 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.920 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.920 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.959 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.959 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.960 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.960 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.960 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.960 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.960 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.960 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.960 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.960 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.961 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.961 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.961 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.961 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.961 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.961 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.961 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.961 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.961 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.961 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.962 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.962 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.962 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.962 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.962 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.962 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:07.962 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.479 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.480 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.518 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.518 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.518 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.557 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.557 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.557 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.596 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.596 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.596 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.634 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.635 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.635 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.674 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.674 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.674 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.713 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.713 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.713 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.752 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.752 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.752 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.792 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.792 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.792 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.830 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.830 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.830 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.869 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.869 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.869 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.908 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.909 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.910 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.949 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.949 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.949 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.988 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.988 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.989 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.989 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.989 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.989 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.989 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.989 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.989 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.989 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.989 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.989 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.989 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.989 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.989 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.990 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.990 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.990 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.990 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.990 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:08.990 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.388 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.388 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.426 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.426 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.426 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.466 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.467 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.468 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.506 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.508 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.548 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.549 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.550 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.589 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.589 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.589 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.630 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.630 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.630 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.669 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.669 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.670 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.709 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.709 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.709 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.747 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.748 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.748 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.787 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.789 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.790 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.828 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.828 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.828 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:09.867 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.173 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 3587
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.174 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.174 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.215 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 53
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.215 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.215 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.216 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.216 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.216 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.216 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.216 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.216 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.216 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.216 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.216 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.216 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.216 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.216 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.217 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.217 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.217 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.217 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.217 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.217 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.217 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.217 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.217 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.217 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.217 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.217 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.666 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.667 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.667 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.667 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.668 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.668 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.669 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.669 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.670 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.670 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.670 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.671 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.671 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.672 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.672 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.673 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.673 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.674 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.674 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.674 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.877 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.877 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.896 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.896 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.897 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:13.984 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.016 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.016 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.050 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.051 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.052 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.086 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.087 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.088 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.121 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.122 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.124 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.157 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.157 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.157 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.191 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.191 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.191 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.225 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.225 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.225 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.259 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.259 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.260 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.260 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.260 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.260 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.260 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.260 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.260 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.261 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.261 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.261 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.261 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.261 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.261 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.261 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.261 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.261 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.262 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.262 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.262 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.262 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.262 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.262 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.262 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.263 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.263 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.708 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.708 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.741 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.741 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.742 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.775 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.777 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.778 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.811 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.811 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.812 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.845 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.845 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.845 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.878 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.879 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.879 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.912 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.912 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.912 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.946 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.947 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.947 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.980 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.980 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:14.980 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.013 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.015 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.016 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.050 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.050 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.050 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.051 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.051 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.051 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.051 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.051 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.051 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.051 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.051 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.051 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.051 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.051 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.051 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.051 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.052 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.052 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.052 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.052 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.052 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.052 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.052 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.052 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.052 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.052 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.052 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.489 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.489 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.496 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.497 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.530 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.530 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.530 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.563 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.564 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.564 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.598 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.598 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.598 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.619 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 3610
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.619 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.620 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.631 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.632 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.632 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.661 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 21
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.662 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.662 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.662 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.662 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.662 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.662 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.662 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.662 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.663 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.663 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.663 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.663 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.663 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.663 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.663 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.663 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.663 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.663 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.663 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.663 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.663 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.664 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.664 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.664 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.664 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.664 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.666 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.666 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.666 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.698 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.699 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.699 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.731 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.731 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.731 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.765 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.765 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.765 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.798 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.798 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.798 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.831 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.831 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.831 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.865 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.866 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.867 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.900 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.900 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.900 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.933 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.933 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.933 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.933 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.934 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.934 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.934 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.934 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.934 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.934 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.934 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.934 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.934 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.934 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.934 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.934 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.935 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.935 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.935 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.935 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:15.935 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.129 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.130 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.131 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.131 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.132 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.132 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.132 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.132 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.132 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.132 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.132 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.132 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.133 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.133 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.133 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.133 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.133 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.133 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.133 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.133 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.277 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.277 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.311 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.311 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.311 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.343 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.345 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.346 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.379 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.380 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.381 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.415 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.416 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.417 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.450 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.451 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.452 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.486 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.487 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.487 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.493 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.493 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.520 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.520 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.520 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.528 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.529 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.529 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.554 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.554 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.554 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.567 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.567 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.567 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.588 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.588 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.589 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.603 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.603 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.603 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.622 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.622 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.622 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.638 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.639 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.639 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.659 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.659 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.660 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.675 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.676 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.676 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.692 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.710 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.710 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.711 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.746 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.746 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.746 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.746 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.747 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.747 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.747 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.747 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.747 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.747 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.747 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.747 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.747 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.747 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.747 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.748 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.748 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.748 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.748 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.748 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.748 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.748 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.748 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.748 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.748 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.748 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:16.749 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.213 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.214 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.248 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.248 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.248 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.283 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.284 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.284 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.320 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.320 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.320 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.355 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.355 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.355 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.390 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.390 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.390 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.425 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.425 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.425 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.459 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.461 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.462 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.496 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.497 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.498 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.533 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.533 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.533 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.568 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.570 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.571 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.571 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.572 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.572 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.572 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.573 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.573 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.573 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.573 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.573 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.573 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.574 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.574 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.574 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.574 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.574 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.574 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.574 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.574 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.574 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.574 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.574 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.574 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.574 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:17.575 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.040 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.041 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.075 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.076 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.076 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.111 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.111 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.112 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.147 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.147 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.147 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.182 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.182 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.182 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.217 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.217 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.217 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.252 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.253 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.253 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.288 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.289 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.290 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.325 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.326 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.326 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.362 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.362 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.362 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.397 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.397 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.397 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.432 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.433 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.433 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.468 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.468 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.469 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.503 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.505 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.506 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.507 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.507 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.507 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.508 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.508 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.508 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.509 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.509 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.509 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.509 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.509 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.509 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.509 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.509 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.509 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.509 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.509 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.509 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.903 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.903 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.904 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.939 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.939 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.939 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.973 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.973 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:18.974 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.010 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.011 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.012 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.047 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.049 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.049 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.084 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.086 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.086 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.121 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.121 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.122 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.156 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.157 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.158 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.193 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.194 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.194 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.229 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.229 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.229 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.264 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.265 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.266 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:19.301 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:20.924 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:20.925 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:20.940 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:20.941 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:20.941 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:20.958 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:20.959 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:20.959 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:20.975 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:20.976 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:20.976 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:20.988 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:20.988 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:20.993 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.069 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.071 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.071 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.084 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.263 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 3538
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.263 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.263 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.311 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 63
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.311 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.311 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.311 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.312 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.312 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.312 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.312 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.312 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.312 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.312 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.312 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.312 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.312 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.312 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.312 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.313 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.313 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.313 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.313 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.313 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.313 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.313 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.313 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.313 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.313 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.313 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.784 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.784 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.854 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.854 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.855 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.855 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.855 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.855 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.855 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.855 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.855 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.855 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.855 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.855 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.855 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.855 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.855 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.856 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.856 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.856 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.856 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:21.856 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.269 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.270 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.311 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.311 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.311 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.355 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.356 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.356 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.397 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.398 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.399 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.439 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.439 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.439 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.479 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.481 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.482 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.522 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.522 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.522 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.563 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.563 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.563 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.563 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.564 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.564 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.564 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.564 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.564 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.564 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.564 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.564 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.564 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.564 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.564 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.564 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.564 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.564 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.565 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.565 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.565 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.565 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.565 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.565 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.565 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.565 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:22.565 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.111 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.111 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.150 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.151 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.152 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.152 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.152 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.170 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.171 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.171 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.188 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.191 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.192 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.192 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.232 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.233 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.234 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.268 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.268 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.268 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.315 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.315 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.315 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.356 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.356 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.357 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.385 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.385 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.385 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.438 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.438 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.439 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.469 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.469 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.469 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.521 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.523 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.524 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.524 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.524 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.524 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.524 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.524 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.524 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.525 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.525 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.525 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.525 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.525 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.525 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.525 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.525 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.525 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.525 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.525 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.525 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.525 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.526 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.526 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.526 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.526 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:23.526 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.064 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.065 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.082 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.082 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.105 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.105 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.105 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.146 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.146 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.146 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.186 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.187 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.187 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.227 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.227 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.227 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.268 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.269 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.269 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.309 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.309 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.309 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.349 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.349 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.349 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.390 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.390 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.390 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.430 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.431 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.431 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.471 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.471 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.471 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.511 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.511 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.511 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.551 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.552 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.552 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.592 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.593 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.593 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.593 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.593 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.593 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.593 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.593 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.593 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.594 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.594 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.594 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.594 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.594 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.594 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.594 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.594 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.594 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.594 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.594 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:24.594 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.009 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.009 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.049 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.049 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.049 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.090 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.090 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.090 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.130 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.130 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.131 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.171 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.173 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.173 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.214 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.214 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.215 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.253 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.254 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.255 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.296 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.296 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.296 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.337 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.337 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.338 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.378 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.378 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.378 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.404 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.420 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.420 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.461 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.462 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.463 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:25.503 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.428 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 3882
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.428 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.428 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.475 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.477 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.477 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.478 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.478 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.479 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.479 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.480 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.480 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.480 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.481 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.482 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.482 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.484 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.484 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.485 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.485 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.486 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.486 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.486 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.487 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.487 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.488 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:35.488 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.006 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.006 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.007 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.007 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.007 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.007 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.007 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.007 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.007 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.007 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.007 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.007 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.007 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.007 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.007 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.007 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.008 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.008 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.008 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.008 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.404 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.404 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.443 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.443 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.443 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.704 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.704 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.704 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.743 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.743 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.743 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.782 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.782 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.782 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.821 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.822 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.823 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.861 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.861 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.861 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.901 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.903 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.904 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.904 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.905 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.905 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.905 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.906 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.906 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.906 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.907 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.907 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.907 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.908 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.908 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.908 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.908 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.909 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.909 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.909 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.910 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.910 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.910 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.911 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.911 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.911 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:36.912 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.430 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.430 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.468 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.470 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.471 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.510 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.510 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.510 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.549 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.550 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.550 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.587 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.588 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.588 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.628 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.628 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.628 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.666 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.668 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.668 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.706 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.707 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.707 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.747 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.747 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.747 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.786 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.786 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.786 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.825 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.825 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.825 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.826 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.826 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.826 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.826 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.826 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.826 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.826 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.826 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.826 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.826 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.826 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.826 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.826 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.827 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.827 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.827 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.827 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.827 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.827 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.827 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.827 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.827 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.827 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:37.827 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.349 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.350 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.389 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.389 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.389 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.428 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.429 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.430 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.470 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.471 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.472 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.510 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.510 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.510 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.550 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.550 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.550 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.588 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.588 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.589 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.628 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.629 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.630 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.669 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.669 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.669 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.709 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.709 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.709 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.747 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.747 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.747 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.786 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.786 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.786 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.825 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.825 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.825 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.864 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.865 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.865 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.865 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.865 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.865 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.865 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.865 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.865 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.865 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.865 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.865 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.866 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.866 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.866 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.866 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.866 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.866 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.866 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.866 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:38.866 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.031 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 4019
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.032 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.032 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 30
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.068 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.263 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.264 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.308 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.308 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.308 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.346 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.346 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.346 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.385 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.387 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.387 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.425 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.426 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.427 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.466 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.466 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.466 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.505 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.506 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.506 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.519 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.519 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.519 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.519 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.519 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.519 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.520 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.520 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.520 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.520 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.520 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.520 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.520 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.520 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.520 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.520 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.521 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.521 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.521 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.521 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.545 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.545 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.545 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.583 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.583 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.583 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.622 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.622 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.622 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.661 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.661 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.661 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.684 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.700 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.701 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.740 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.865 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.866 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.885 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.885 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.885 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.931 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.932 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.932 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.965 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.966 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.966 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:39.999 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.000 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.001 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.034 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.035 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.035 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.069 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.070 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.070 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.106 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.106 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.107 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.107 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.107 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.107 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.107 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.107 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.107 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.107 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.107 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.107 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.108 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.108 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.108 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.108 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.108 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.108 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.108 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.108 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.108 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.108 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.108 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.109 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.109 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.109 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.109 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.555 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.555 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.588 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.589 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.589 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.606 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 4108
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.606 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.606 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.622 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.622 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.622 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.649 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 21
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.649 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.649 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.649 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.649 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.649 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.650 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.650 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.650 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.650 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.650 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.650 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.650 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.650 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.650 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.650 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.650 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.650 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.650 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.651 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.651 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.651 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.651 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.651 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.651 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.651 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.651 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.655 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.655 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.655 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.688 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.689 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.689 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.722 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.722 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.722 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.756 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.756 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.756 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.789 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.789 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.789 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.823 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.823 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.823 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.856 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.856 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.856 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.890 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.890 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.890 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.891 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.891 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.891 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.891 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.891 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.891 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.891 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.891 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.891 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.891 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.891 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.891 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.892 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.892 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.892 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.892 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.892 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.892 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.892 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.892 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.892 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.892 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.892 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:40.892 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.117 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.117 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.117 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.117 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.118 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.118 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.118 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.118 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.118 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.118 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.118 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.118 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.118 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.118 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.118 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.118 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.118 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.119 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.119 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.119 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.372 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.373 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.406 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.406 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.407 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.440 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.440 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.440 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.474 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.474 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.474 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.500 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.500 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.507 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.507 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.507 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.534 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.535 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.535 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.540 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.540 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.540 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.571 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.571 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.571 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.574 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.574 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.574 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.605 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.605 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.606 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.608 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.608 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.608 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.641 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.641 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.641 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.641 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.642 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.642 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.674 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.674 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.674 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.676 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.676 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.676 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.708 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.708 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.708 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.710 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.710 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.710 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.742 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.742 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.742 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.745 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.745 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.745 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.745 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.745 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.745 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.746 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.746 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.746 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.746 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.746 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.746 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.746 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.746 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.746 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.746 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.746 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.746 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.746 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.746 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.747 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.747 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.747 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.747 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.747 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.747 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.747 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.775 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.775 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.775 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.809 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.810 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.810 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.810 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.810 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.811 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.811 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.811 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.811 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.812 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.812 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.812 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.812 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.812 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.813 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.813 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.813 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.813 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.813 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.814 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:41.814 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.155 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.156 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.190 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.190 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.190 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.211 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.211 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.223 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.223 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.223 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.246 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.247 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.248 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.257 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.258 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.259 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.282 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.282 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.282 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.291 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.291 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.291 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.317 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.317 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.317 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.325 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.326 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.327 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.352 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.352 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.353 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.360 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.360 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.361 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.387 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.387 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.387 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.394 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.394 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.394 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.422 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.423 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.423 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.427 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.427 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.427 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.457 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.458 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.458 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.460 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.460 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.460 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.492 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.492 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.492 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.494 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.494 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.494 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.527 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.527 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.527 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.527 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.528 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.528 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.561 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.562 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.563 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.563 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.563 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.564 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.564 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.564 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.564 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.565 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.565 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.565 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.565 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.565 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.566 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.566 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.566 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.566 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.566 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.567 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.567 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.567 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.567 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.567 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.568 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.568 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.568 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:42.568 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.042 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.043 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.072 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.072 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.072 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.113 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.113 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.113 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.148 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.148 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.148 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.182 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.184 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.184 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.206 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.221 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.221 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.256 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.257 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.257 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.292 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.292 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.292 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.322 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.322 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.322 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.363 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.363 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.363 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.398 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.398 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.398 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.433 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.433 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.433 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.468 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.468 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.469 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.502 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.503 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.503 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.503 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.503 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.504 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.504 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.504 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.504 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.504 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.504 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.504 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.504 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.504 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.504 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.504 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.504 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.504 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.505 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.505 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.505 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.861 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.862 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.897 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.897 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.897 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.932 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.933 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.934 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.956 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.956 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:43.956 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.006 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.006 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.006 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.041 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.041 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.041 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.076 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.077 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.077 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.112 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.113 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.113 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.147 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.148 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.148 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.182 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.183 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.183 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.218 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.218 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.218 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.253 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.253 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.253 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:44.287 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:49.060 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:49.060 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:49.078 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:49.080 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:49.081 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:49.097 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:49.395 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:49.395 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:52.645 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:52.645 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:52.663 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:52.665 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:52.665 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:52.683 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:53.326 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:53.326 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.431 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 4524
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.432 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.432 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 75
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.487 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.487 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.953 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.953 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.953 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.953 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.953 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.953 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.953 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.953 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.953 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.954 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.954 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.954 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.954 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.954 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.954 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.954 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.954 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.954 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.954 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:29:59.954 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.315 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.315 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.351 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.351 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.351 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.386 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.387 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.388 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.422 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.424 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.425 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.460 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.460 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.460 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.495 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.496 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.496 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.532 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.532 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.533 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.567 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.567 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.567 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.568 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.568 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.568 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.568 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.568 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.568 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.568 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.568 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.568 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.568 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.568 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.568 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.568 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.569 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.569 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.569 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.569 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.569 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.569 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.569 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.569 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.569 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.569 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:00.569 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.036 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.036 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.071 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.071 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.072 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.105 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.106 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.106 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.141 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.143 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.144 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.179 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.179 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.179 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.207 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.207 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.207 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.249 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.249 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.249 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.284 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.285 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.285 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.320 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.320 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.320 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.355 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.355 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.355 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.390 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.390 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.390 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.391 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.391 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.391 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.391 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.391 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.391 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.391 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.391 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.391 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.391 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.392 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.392 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.392 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.392 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.392 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.392 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.392 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.392 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.392 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.392 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.392 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.392 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.392 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.393 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.873 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.873 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.907 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.907 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.907 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.938 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.938 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.938 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.980 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.980 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:01.980 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.015 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.016 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.017 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.052 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.053 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.054 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.089 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.090 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.090 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.124 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.124 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.124 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.159 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.159 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.160 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.193 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.194 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.194 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.229 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.229 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.229 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.264 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.264 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.264 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.299 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.300 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.301 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.336 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.336 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.336 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.337 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.337 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.337 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.337 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.337 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.337 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.337 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.337 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.337 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.337 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.337 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.337 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.337 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.338 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.338 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.338 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.338 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.338 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.695 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.695 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.730 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.731 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.731 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.765 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.766 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.766 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.800 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.801 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.801 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.835 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.835 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.835 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.870 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.871 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.872 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.906 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.907 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.907 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.942 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.943 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.943 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.978 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.978 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:02.978 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:03.013 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:03.013 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:03.013 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:03.048 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:03.048 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:03.048 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:03.087 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:03.088 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:03.088 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:03.122 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.524 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 4524
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.525 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.525 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.567 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.567 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.567 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.567 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.568 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.568 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.568 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.568 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.568 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.568 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.568 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.568 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.568 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.568 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.568 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.568 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.569 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.569 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.569 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.569 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.569 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.569 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.569 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.569 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.569 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.569 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:04.569 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.021 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.021 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.022 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.022 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.023 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.023 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.024 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.024 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.024 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.024 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.024 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.024 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.024 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.024 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.024 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.025 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.025 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.025 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.025 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.025 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.370 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.370 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.404 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.404 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.404 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.439 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.440 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.441 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.474 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.475 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.475 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.508 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.508 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.508 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.542 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.542 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.543 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.575 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.576 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.576 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.609 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.609 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.610 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.610 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.610 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.610 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.610 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.610 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.610 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.610 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.610 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.610 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.611 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.611 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.611 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.611 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.611 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.611 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.611 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.611 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.611 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.611 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.611 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.612 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.612 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.612 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:05.612 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.063 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.064 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.096 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.098 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.099 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.129 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.129 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.129 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.168 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.168 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.168 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.235 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.235 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.235 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.269 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.270 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.271 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.304 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.304 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.304 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.338 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.338 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.338 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.372 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.372 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.372 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.405 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.407 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.407 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.407 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.408 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.408 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.408 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.408 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.408 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.408 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.408 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.408 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.408 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.408 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.408 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.408 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.408 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.408 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.409 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.409 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.409 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.409 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.409 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.409 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.409 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.409 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.409 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.845 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.845 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.889 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.890 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.890 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.922 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.924 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.958 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.959 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.960 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.993 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.994 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:06.994 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.028 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.029 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.029 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.063 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.064 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.064 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.096 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.097 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.097 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.131 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.131 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.131 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.161 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.161 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.161 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.199 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.199 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.199 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.232 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.232 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.232 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.261 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.261 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.261 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.299 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.300 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.300 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.300 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.300 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.300 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.300 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.301 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.301 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.301 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.301 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.301 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.301 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.301 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.301 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.301 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.302 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.302 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.302 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.302 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.302 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.646 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.646 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.679 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.679 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.680 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.713 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.713 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.713 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.746 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.747 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.747 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.780 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.781 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.782 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.816 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.818 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.818 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.845 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.845 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.845 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.885 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.885 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.885 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.913 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.913 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.913 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.952 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.952 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.952 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.986 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.986 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:07.986 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:08.019 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:08.019 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:08.019 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:08.053 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:38.908 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:38.908 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:38.924 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:38.924 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:38.925 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:38.941 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:38.942 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:38.942 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:38.948 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:38.949 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:38.958 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:38.958 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:38.958 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:38.966 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:38.966 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:38.966 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:38.974 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:38.984 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:39.266 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:39.266 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:43.591 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:43.591 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:43.607 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:43.608 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:43.608 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:43.624 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:43.644 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:43.644 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:43.661 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:43.661 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:43.661 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:43.677 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:44.535 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:44.535 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:44.954 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:44.954 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:45.476 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:45.477 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:45.496 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:45.497 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:45.497 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:45.517 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.809 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 4717
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.809 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.809 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.811 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.811 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.854 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.854 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.854 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.854 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.855 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.855 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.855 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.855 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.855 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.855 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.855 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.855 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.855 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.855 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.855 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.855 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.855 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.856 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.856 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.856 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.856 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.856 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.856 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.856 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.856 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.856 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:50.857 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.326 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.327 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.327 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.327 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.327 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.327 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.327 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.327 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.327 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.327 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.327 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.328 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.328 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.328 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.328 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.328 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.328 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.328 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.328 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.328 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.689 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.689 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.724 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.726 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.726 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.761 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.762 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.763 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.797 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.799 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.799 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.835 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.835 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.835 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.870 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.870 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.870 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.904 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.905 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.906 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.940 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.942 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.942 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.942 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.943 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.943 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.943 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.943 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.944 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.944 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.944 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.944 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.944 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.944 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.945 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.945 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.945 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.945 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.945 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.946 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.946 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.946 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.946 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.946 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.946 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.946 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:51.947 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.192 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.192 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.284 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.286 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.286 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.306 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.443 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.444 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.479 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.479 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.479 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.514 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.514 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.514 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.550 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.550 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.550 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.585 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.585 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.585 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.620 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.621 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.621 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.656 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.656 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.656 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.692 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.693 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.694 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.729 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.729 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.729 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.764 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.764 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.764 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.799 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.800 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.800 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.800 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.800 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.800 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.800 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.801 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.801 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.801 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.801 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.801 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.801 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.801 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.801 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.801 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.801 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.801 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.802 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.802 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.802 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.802 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.802 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.802 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.802 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.802 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:52.802 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.268 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.268 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.303 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.303 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.303 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.338 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.338 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.338 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.373 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.373 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.373 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.408 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.408 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.408 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.443 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.443 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.443 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.478 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.478 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.478 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.513 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.513 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.513 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.548 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.548 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.548 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.582 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.583 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.583 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.612 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.613 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.618 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.618 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.618 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.653 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.654 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.655 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.690 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.692 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.693 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.727 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.728 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.728 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.728 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.728 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.728 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.728 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.728 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.729 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.729 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.729 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.729 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.729 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.729 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.729 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.729 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.729 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.729 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.729 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.729 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:53.729 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.087 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.087 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.122 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.123 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.123 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.157 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.158 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.158 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.192 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.193 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.193 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.228 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.228 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.229 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.264 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.265 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.265 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.299 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.300 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.300 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.335 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.336 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.336 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.372 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.373 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.373 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.408 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.408 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.408 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.444 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.445 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.446 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.479 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.480 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.480 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.516 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.967 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.967 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.985 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.985 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:54.985 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:55.002 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:56.157 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:30:56.157 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.430 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 4717
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.431 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.431 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.485 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.485 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.485 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.486 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.486 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.486 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.486 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.486 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.486 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.486 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.486 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.486 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.486 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.486 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.486 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.486 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.487 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.487 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.487 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.487 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.487 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.487 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.487 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.487 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.487 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.487 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.487 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.979 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.979 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.980 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.980 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.980 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.980 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.980 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.981 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.981 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.981 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.981 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.981 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.982 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.982 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.982 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.982 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.983 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.983 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.983 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:14.983 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.587 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.587 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.622 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.622 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.622 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.631 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.631 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.631 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.674 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.674 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.674 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.691 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.691 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.691 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.724 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.724 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.725 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.748 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.748 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.748 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.796 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.797 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.797 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.830 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.831 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.832 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.867 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.868 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.869 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.869 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.869 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.869 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.869 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.869 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.869 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:15.869 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.356 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.357 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.390 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.390 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.390 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.424 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.424 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.424 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.457 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.458 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.459 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.493 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.495 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.495 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.528 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.529 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.530 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.564 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.564 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.564 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.597 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.598 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.598 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.631 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.631 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.631 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.664 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.665 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.666 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.699 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.700 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.700 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.700 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.700 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.700 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.700 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.700 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.700 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.700 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.700 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.700 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.700 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.701 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.701 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.701 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.701 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.701 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.701 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.701 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.701 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.701 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.701 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.701 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.701 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.701 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:16.701 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.149 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.149 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.182 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.185 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.186 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.219 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.219 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.219 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.253 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.253 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.253 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.282 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.282 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.282 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.324 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.324 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.324 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.358 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.359 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.360 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.393 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.393 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.393 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.427 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.428 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.428 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.461 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.461 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.461 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.495 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.495 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.495 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.516 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.516 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.516 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.563 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.563 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.563 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.597 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.597 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.597 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.597 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.597 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.597 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.597 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.598 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.598 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.598 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.598 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.598 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.598 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.598 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.598 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.598 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.598 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.598 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.598 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.599 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.599 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.985 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:17.986 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.020 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.020 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.020 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.053 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.055 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.056 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.089 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.090 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.090 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.123 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.123 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.123 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.156 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.157 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.157 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.190 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.191 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.191 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.223 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.224 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.224 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.257 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.258 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.258 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.291 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.291 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.291 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.325 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.325 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.325 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.358 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.359 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.359 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.392 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.459 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:18.459 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:20.352 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:20.352 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:20.375 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:20.376 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:20.376 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:20.458 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:21.178 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:21.178 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.142 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 4717
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.143 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.143 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.194 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.194 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.194 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.194 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.196 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.196 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.196 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.196 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.196 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.196 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.196 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.196 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.196 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.196 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.196 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.735 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.735 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.736 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.736 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.736 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.736 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.736 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.736 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.736 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.736 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.736 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.736 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.736 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.736 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.736 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.736 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.737 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.737 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.737 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:30.737 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.156 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.157 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.197 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.197 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.197 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.240 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.240 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.240 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.281 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.281 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.281 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.322 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.322 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.322 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.363 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.363 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.363 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.406 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.406 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.406 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.446 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.983 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:31.983 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.027 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.027 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.027 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.068 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.068 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.068 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.109 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.109 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.110 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.150 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.150 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.150 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.191 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.191 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.191 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.232 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.232 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.233 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.272 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.273 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.273 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.313 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.314 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.314 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.356 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.357 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.397 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.397 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.397 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.398 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.398 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.398 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.398 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.398 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.398 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.398 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.398 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.398 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.398 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.398 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.398 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.399 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.399 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.399 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.399 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.399 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.399 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.399 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.399 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.399 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.399 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.399 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.399 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.608 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 4796
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.609 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.609 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.659 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.661 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.661 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.662 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.662 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.663 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.663 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.663 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.664 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.664 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.664 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.664 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.664 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.664 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.665 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.665 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.665 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.665 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.665 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.665 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.665 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.665 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.665 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.665 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.665 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.665 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.665 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.938 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.938 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.979 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.980 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:32.980 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.020 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.020 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.020 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.060 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.061 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.061 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.102 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.102 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.102 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.142 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.142 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.143 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.182 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.183 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.183 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.210 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.211 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.211 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.211 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.211 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.211 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.211 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.211 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.211 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.211 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.211 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.211 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.211 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.211 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.212 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.212 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.212 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.212 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.212 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.212 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.223 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.224 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.224 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.263 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.264 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.264 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.304 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.304 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.304 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.345 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.345 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.345 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.384 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.385 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.385 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.425 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.425 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.425 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.464 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.465 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.465 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.465 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.466 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.466 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.466 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.466 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.466 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.466 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.466 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.466 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.466 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.466 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.466 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.466 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.466 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.467 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.467 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.467 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.467 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.630 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.631 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.672 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.673 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.673 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.717 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.718 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.718 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.758 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.759 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.759 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.800 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.800 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.800 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.842 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.842 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.842 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.882 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.883 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.883 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.884 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.923 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.924 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.924 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.924 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.924 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.924 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.924 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.924 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.924 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.925 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.925 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.925 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.925 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.925 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.925 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.925 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.925 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.925 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.925 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.925 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.925 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.925 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.926 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.926 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.926 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.926 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.926 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.926 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.926 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.926 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.964 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.965 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:33.966 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.006 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.006 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.006 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.047 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.047 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.047 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.083 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.083 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.083 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.127 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.127 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.128 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.165 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.165 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.165 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.202 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.202 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.202 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.248 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.250 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.250 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.283 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.283 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.283 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.330 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.331 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.331 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.367 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.471 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.471 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.512 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.512 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.512 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.550 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.550 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.550 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.584 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.584 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.584 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.634 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.634 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.634 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.678 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.678 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.678 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.720 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.720 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.720 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.762 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.764 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.765 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.806 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.806 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.806 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.847 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.847 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.847 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:34.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.437 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.437 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.479 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.479 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.479 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.520 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.521 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.521 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.563 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.564 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.564 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.605 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.605 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.605 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.646 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.647 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.647 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.687 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.688 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.688 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.728 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.729 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.730 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.770 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.771 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.771 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.812 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.812 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.812 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.853 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.854 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.854 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.894 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.894 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.895 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.936 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.937 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.937 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.977 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.978 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.978 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.978 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.978 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.978 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.978 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.978 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.978 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.978 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.978 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.979 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.979 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.979 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.979 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.979 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.979 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.979 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.979 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.979 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:35.979 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.398 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.398 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.440 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.440 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.441 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.482 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.483 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.484 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.519 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.519 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.519 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.568 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.568 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.569 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.610 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.612 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.613 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.653 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.654 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.655 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.685 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.685 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.685 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.737 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.739 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.739 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.779 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.779 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.781 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.820 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.820 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.820 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.862 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.862 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.863 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.902 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.952 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 4717
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.952 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:36.952 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.009 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 67
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.009 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.009 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.009 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.010 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.010 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.010 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.010 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.010 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.010 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.010 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.010 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.010 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.010 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.010 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.010 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.010 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.011 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.011 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.011 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.011 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.011 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.011 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.011 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.011 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.011 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.011 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.538 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.538 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.539 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.539 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.539 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.539 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.539 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.539 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.539 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.539 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.539 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.539 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.539 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.539 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.540 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.540 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.540 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.540 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.540 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.540 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.938 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.938 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.976 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.977 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:37.977 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.007 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.007 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.007 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.056 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.058 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.058 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.096 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.097 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.098 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.137 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.138 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.138 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.177 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.177 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.178 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.218 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.218 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.218 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.218 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.218 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.218 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.218 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.218 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.218 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.218 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.218 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.219 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.219 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.219 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.219 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.219 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.219 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.219 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.219 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.219 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.219 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.219 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.220 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.220 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.220 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.220 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.220 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.740 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.741 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.780 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.781 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.782 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.822 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.822 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.823 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.861 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.861 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.861 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.899 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.901 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.901 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.941 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.941 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.942 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.980 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.980 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:38.980 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.019 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.019 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.019 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.059 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.059 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.059 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.097 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.099 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.100 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.139 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.139 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.140 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.140 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.140 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.140 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.140 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.140 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.140 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.140 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.140 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.140 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.140 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.140 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.141 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.141 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.141 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.141 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.141 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.141 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.141 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.141 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.141 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.141 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.141 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.141 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.141 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.661 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.661 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.701 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.701 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.702 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.740 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.740 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.741 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.779 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.781 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.781 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.820 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.821 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.822 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.861 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.861 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.861 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.900 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.901 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.901 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.939 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.940 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.940 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.979 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.981 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:39.982 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.020 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.021 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.021 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.060 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.061 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.061 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.100 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.100 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.100 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.138 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.139 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.139 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.178 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.178 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.178 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.178 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.179 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.179 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.179 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.179 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.179 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.179 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.179 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.179 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.179 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.179 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.179 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.179 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.179 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.180 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.180 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.180 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.180 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.582 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.582 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.621 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.621 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.621 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.660 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.661 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.662 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.701 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.702 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.702 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.741 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.742 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.743 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.781 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.782 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.782 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.821 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.823 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.824 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.863 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.863 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.863 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.902 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.902 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.902 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.941 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.942 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.942 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.980 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.981 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:40.981 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:41.019 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:41.020 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:41.020 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:41.060 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.127 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 4943
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.128 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.128 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.171 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.173 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.173 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.174 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.174 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.175 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.175 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.176 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.176 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.176 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.177 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.177 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.178 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.178 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.178 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.179 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.179 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.180 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.180 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.180 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.181 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.181 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.182 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.182 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.182 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.183 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.183 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.633 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.634 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.634 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.634 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.634 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.634 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.634 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.634 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.634 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.634 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.635 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.635 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.635 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.635 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.635 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.635 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.635 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.635 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.635 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.635 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.982 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:42.982 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.016 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.017 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.018 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.052 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.052 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.052 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.086 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.086 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.086 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.108 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.108 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.108 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.153 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.153 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.153 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.186 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.188 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.189 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.223 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.223 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.223 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.223 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.224 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.224 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.224 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.224 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.224 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.224 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.224 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.224 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.224 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.224 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.225 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.225 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.225 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.225 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.225 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.225 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.225 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.225 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.225 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.225 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.225 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.225 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.225 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.674 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.674 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.707 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.707 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.708 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.740 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.741 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.741 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.774 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.775 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.775 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.794 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.810 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.810 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.843 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.843 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.843 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.876 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.877 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.877 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.909 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.909 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.909 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.943 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.944 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.944 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.978 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.978 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:43.978 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.012 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.012 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.012 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.013 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.013 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.013 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.013 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.013 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.013 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.013 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.013 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.013 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.013 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.013 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.013 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.013 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.013 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.014 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.014 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.014 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.014 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.014 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.014 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.014 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.014 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.014 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.014 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.464 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.464 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.498 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.498 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.499 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.531 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.531 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.532 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.564 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.565 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.565 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.569 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 4943
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.569 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.569 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.599 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.600 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.600 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.615 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 21
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.616 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.617 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.617 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.617 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.618 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.618 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.618 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.619 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.619 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.619 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.619 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.620 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.620 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.620 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.621 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.621 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.621 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.621 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.622 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.622 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.622 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.622 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.622 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.623 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.623 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.623 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.634 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.634 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.634 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.666 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.667 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.667 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.700 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.701 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.701 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.734 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.734 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.734 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.767 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.769 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.770 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.804 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.804 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.804 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.836 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.837 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.837 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.870 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.871 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.871 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.905 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.906 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.906 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.906 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.906 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.906 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.906 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.906 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.906 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.906 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.906 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.907 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.907 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.907 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.907 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.907 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.907 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.907 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.907 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.907 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:44.907 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.105 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.105 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.105 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.105 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.105 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.105 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.105 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.105 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.105 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.106 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.106 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.106 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.106 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.106 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.106 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.106 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.106 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.106 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.106 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.106 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.244 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.244 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.284 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.284 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.284 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.318 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.319 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.320 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.353 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.353 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.353 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.386 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.386 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.386 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.420 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.420 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.420 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.443 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.443 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.443 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.461 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.461 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.477 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.477 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.477 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.510 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.510 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.510 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.510 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.510 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.510 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.547 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.547 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.547 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.554 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.554 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.554 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.584 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.586 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.586 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.587 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.589 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.589 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.623 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.623 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.623 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.623 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.624 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.624 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.656 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.656 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.657 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.660 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.690 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.690 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.690 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.723 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.723 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.723 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.724 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.724 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.724 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.724 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.724 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.724 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.724 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.724 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.724 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.724 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.724 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.724 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.724 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.725 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.725 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.725 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.725 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.725 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.725 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.725 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.725 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.725 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.725 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:45.725 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.402 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.403 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.437 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.438 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.439 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.480 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.481 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.482 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.519 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.519 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.519 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.553 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.555 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.555 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.589 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.590 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.591 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.625 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.625 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.625 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.659 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.660 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.660 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.693 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.693 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.694 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.727 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.727 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.727 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.761 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.761 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.762 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.762 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.762 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.762 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.762 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.762 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.762 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.762 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.763 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.763 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.763 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.763 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.763 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.763 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.763 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.763 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.764 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.764 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.764 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.764 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.764 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.764 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.764 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.764 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:46.764 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.210 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.210 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.243 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.245 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.246 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.279 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.279 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.279 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.312 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.314 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.315 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.349 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.349 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.349 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.383 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.383 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.383 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.417 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.417 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.417 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.450 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.451 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.451 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.484 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.484 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.484 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.517 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.518 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.518 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.551 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.552 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.552 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.584 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.585 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.585 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.618 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.618 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.619 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.652 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.653 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.654 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.655 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.655 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.656 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.656 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.657 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.657 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.657 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.657 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.657 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.657 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.657 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.657 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.657 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.657 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.657 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.658 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.658 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.658 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.793 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 4830
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.794 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.794 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.837 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 51
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.838 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.838 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.838 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.839 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.839 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.839 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.839 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.839 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.839 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.839 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.839 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.839 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.839 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.839 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.840 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.840 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.840 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.840 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.840 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.840 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.840 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.840 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.840 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.840 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.840 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.840 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.997 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:47.997 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.030 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.030 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.030 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.064 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.065 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.065 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.097 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.098 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.098 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.131 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.132 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.132 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.165 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.165 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.166 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.197 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.197 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.197 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.233 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.234 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.234 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.266 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.267 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.267 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.300 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.300 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.301 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.302 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.302 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.303 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.303 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.303 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.303 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.303 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.303 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.303 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.303 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.303 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.303 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.303 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.303 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.303 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.304 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.304 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.304 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.304 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.304 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.334 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.334 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.334 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.367 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.367 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.367 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.397 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.664 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.664 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.698 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.701 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.701 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.736 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.737 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.738 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.764 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.764 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.764 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.809 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.809 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.809 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.831 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.831 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.831 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.879 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.880 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.880 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.913 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.914 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.915 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.915 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.915 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.915 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.915 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.915 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.915 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.915 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.915 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.915 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.915 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.915 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.915 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.916 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.916 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.916 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.916 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.916 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.916 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.916 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.916 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.916 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.916 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.916 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:48.916 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.388 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.389 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.423 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.424 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.425 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.461 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.463 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.463 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.498 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.500 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.500 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.535 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.536 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.537 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.572 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.574 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.575 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.609 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.611 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.612 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.647 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.647 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.648 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.682 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.683 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.684 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.719 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.720 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.720 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.756 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.756 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.757 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.757 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.757 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.757 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.757 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.757 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.757 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.757 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.758 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.758 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.758 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.758 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.758 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.758 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.758 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.758 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.758 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.758 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.758 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.758 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.758 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.758 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.759 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.759 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:49.759 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.223 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.223 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.258 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.258 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.258 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.293 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.293 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.293 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.328 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.328 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.328 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.363 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.363 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.363 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.399 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.400 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.400 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.435 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.435 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.436 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.470 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.471 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.471 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.505 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.505 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.506 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.541 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.541 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.541 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.576 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.576 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.576 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.612 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.612 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.612 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.655 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.656 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.657 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.692 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.692 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.692 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.692 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.693 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.693 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.693 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.693 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.693 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.693 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.693 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.693 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.693 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.693 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.693 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.693 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.693 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.694 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.694 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.694 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:50.694 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.052 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.052 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.087 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.088 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.089 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.124 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.124 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.124 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.159 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.160 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.160 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.195 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.195 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.195 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.230 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.232 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.232 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.266 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.267 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.267 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.302 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.303 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.303 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.338 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.338 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.338 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.372 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.372 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.373 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.408 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.408 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.408 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.443 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.443 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.443 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:31:51.477 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:14.904 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:14.904 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:14.921 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:14.922 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:14.922 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:14.938 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:14.939 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:14.939 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:14.955 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:14.956 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:14.956 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:14.973 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:14.986 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:14.986 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:15.004 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:15.004 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:15.004 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:15.021 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:15.300 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:15.300 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.895 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 5633
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.896 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.896 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.942 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 54
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.942 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.942 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.943 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.943 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.943 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.943 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.943 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.943 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.943 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.943 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.943 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.943 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.943 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.943 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.944 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.944 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.944 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.944 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.944 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.944 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.944 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.944 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.944 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.944 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.944 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:23.944 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.423 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.423 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.423 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.423 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.426 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.426 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.427 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.427 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.427 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.427 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.427 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.427 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.427 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.428 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.428 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.428 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.428 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.428 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.428 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.428 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.786 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.786 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.820 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.821 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.821 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.855 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.855 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.855 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.882 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.882 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.882 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.926 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.926 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.950 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.950 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.950 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.984 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.984 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:24.984 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.030 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.031 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.031 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.031 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.031 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.031 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.031 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.031 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.031 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.031 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.031 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.032 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.032 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.032 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.032 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.032 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.032 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.032 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.032 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.032 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.033 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.033 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.033 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.033 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.033 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.033 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.033 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.500 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.500 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.535 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.536 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.537 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.571 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.571 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.571 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.605 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.606 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.606 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.640 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.641 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.641 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.676 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.676 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.676 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.712 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.712 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.712 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.747 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.747 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.747 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.781 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.782 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.782 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.817 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.819 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.819 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.854 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.854 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.855 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.855 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.855 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.855 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.855 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.855 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.855 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.855 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.855 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.855 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.855 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.855 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.855 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.855 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.856 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.856 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.856 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.856 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.856 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.856 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.856 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.856 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.856 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.856 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:25.856 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.323 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.359 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.359 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.359 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.394 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.394 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.395 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.429 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.430 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.430 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.465 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.467 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.467 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.502 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.502 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.502 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.537 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.538 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.538 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.573 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.573 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.574 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.607 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.608 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.608 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.643 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.645 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.645 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.679 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.680 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.681 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.715 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.716 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.716 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.750 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.750 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.750 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.786 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.786 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.788 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.788 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.788 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.788 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.788 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.788 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:26.788 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.144 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.144 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.179 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.180 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.180 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.214 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.214 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.214 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.249 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.249 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.249 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.284 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.284 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.285 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.319 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.320 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.320 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.390 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.390 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.390 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.425 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.425 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.425 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.460 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.460 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.460 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.495 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.495 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.495 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.530 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.530 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.531 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:27.566 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:50.446 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:50.446 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:50.463 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:50.464 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:50.464 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:50.482 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:50.754 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:50.755 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.909 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 5734
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.910 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.910 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.956 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.957 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.957 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.957 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.957 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.957 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.957 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.957 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.957 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.958 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.958 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.958 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.958 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.958 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.958 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.958 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.958 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.958 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.958 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.958 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.958 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.959 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.959 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.959 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.959 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.959 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:32:59.959 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.424 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.424 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.424 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.424 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.424 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.424 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.425 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.425 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.425 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.425 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.425 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.425 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.425 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.425 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.425 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.425 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.425 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.425 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.425 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.426 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.786 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.786 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.821 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.823 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.823 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.858 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.858 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.859 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.893 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.893 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.894 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.928 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.930 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.930 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.966 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.967 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:00.968 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.002 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.003 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.003 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.038 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.039 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.039 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.039 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.039 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.039 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.039 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.039 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.040 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.040 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.040 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.040 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.040 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.040 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.040 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.040 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.040 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.040 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.041 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.041 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.041 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.041 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.041 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.041 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.041 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.042 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.042 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.511 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.512 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.547 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.547 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.547 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.582 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.582 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.582 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.606 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.606 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.606 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.652 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.654 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.655 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.686 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.686 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.686 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.726 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.726 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.726 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.754 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.754 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.754 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.797 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.798 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.799 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.834 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.835 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.835 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.869 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.870 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.870 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.870 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.870 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.870 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.870 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.870 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.870 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.870 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.870 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.870 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.871 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.871 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.871 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.871 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.871 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.871 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.871 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.871 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.871 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.871 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.871 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.871 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.871 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.871 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:01.872 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.340 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.341 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.376 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.377 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.377 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.412 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.412 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.413 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.447 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.447 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.447 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.482 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.482 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.483 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.518 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.518 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.518 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.553 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.553 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.554 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.588 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.588 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.588 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.623 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.624 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.624 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.659 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.659 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.659 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.694 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.694 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.694 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.730 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.730 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.730 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.765 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.766 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.766 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.801 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.801 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.802 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.802 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.802 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.802 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.802 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.802 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.802 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.802 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.802 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.802 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.803 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.803 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.803 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.803 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.803 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.803 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.803 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.803 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:02.803 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.155 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.155 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.196 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.196 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.196 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.231 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.231 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.231 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.266 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.266 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.267 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.301 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.301 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.301 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.336 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.337 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.337 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.363 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.363 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.363 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.405 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.405 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.405 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.437 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.437 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.437 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.479 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.479 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.479 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.514 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.514 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.514 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.550 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.550 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.550 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:33:03.584 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.050 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.050 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.066 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.066 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.066 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.084 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.084 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.084 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.102 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.104 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.105 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.121 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.122 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.123 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.140 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.140 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.140 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.157 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.433 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:07.433 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.942 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 5847
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.942 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.943 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.990 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.990 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.991 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.991 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.991 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.991 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.991 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.991 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.991 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.991 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.991 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.991 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.991 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.991 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.992 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.992 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.992 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.992 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.992 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.992 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.992 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.992 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.992 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.992 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.992 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.992 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:14.992 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.460 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.460 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.460 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.461 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.461 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.461 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.461 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.462 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.462 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.462 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.462 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.462 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.463 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.463 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.463 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.463 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.463 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.464 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.464 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.464 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.824 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.824 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.859 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.860 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.861 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.897 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.897 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.897 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.932 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.932 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.932 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.967 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.967 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:15.968 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.002 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.003 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.004 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.038 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.040 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.040 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.075 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.075 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.075 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.076 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.076 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.076 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.076 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.076 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.076 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.076 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.076 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.076 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.076 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.077 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.077 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.077 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.077 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.077 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.077 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.077 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.077 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.077 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.077 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.077 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.078 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.078 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.078 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.545 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.546 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.580 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.582 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.583 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.618 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.618 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.618 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.673 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.675 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.675 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.711 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.712 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.712 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.750 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.750 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.750 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.785 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.785 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.786 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.820 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.820 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.820 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.844 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.844 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.844 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.891 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.892 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.892 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.927 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.928 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.929 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.929 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.929 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.929 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.929 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.929 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.929 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.929 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.929 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.929 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.929 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.929 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.930 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.930 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.930 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.930 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.930 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.930 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.930 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.930 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.930 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.930 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.930 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.930 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:16.930 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.397 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.397 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.431 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.432 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.432 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.467 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.467 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.467 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.502 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.503 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.503 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.537 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.538 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.538 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.574 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.575 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.576 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.611 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.613 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.614 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.648 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.649 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.649 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.683 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.683 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.683 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.718 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.718 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.718 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.754 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.756 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.757 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.792 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.792 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.792 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.827 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.828 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.828 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.862 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.863 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.863 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.863 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.863 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.863 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.863 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.864 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.864 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.864 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.864 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.864 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.864 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.864 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.864 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.864 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.864 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.864 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.864 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.864 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:17.865 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.222 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.223 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.257 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.258 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.258 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.293 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.293 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.294 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.329 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.329 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.330 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.364 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.365 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.366 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.400 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.401 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.401 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.435 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.436 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.436 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.471 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.471 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.472 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.506 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.507 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.507 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.542 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.542 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.542 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.577 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.577 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.577 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.612 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.613 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.614 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:18.648 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:38.219 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:38.219 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:38.236 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:38.236 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:38.237 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:38.254 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:38.491 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:38.491 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.682 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 5960
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.683 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.683 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.728 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.729 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.729 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.729 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.729 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.729 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.729 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.729 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.729 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.729 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.730 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.730 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.730 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.730 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.730 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.730 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.730 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.730 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.730 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.730 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.730 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.730 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.731 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.731 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.731 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.731 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:47.731 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.201 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.202 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.202 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.202 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.202 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.202 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.202 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.202 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.202 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.202 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.202 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.202 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.203 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.203 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.203 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.203 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.203 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.203 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.203 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.203 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.563 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.564 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.594 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.594 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.594 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.636 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.638 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.638 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.673 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.675 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.675 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.710 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.710 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.710 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.745 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.745 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.745 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.785 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.786 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.786 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.821 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.823 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.824 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.824 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.824 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.825 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.826 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.826 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.827 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.827 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.828 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.829 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.829 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.830 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.830 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.831 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.831 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.831 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.832 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.832 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.833 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.833 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.833 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.834 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.834 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.835 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:48.835 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.305 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.305 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.328 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.328 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.328 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.377 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.378 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.378 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.415 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.415 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.416 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.444 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.444 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.444 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.486 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.486 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.486 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.521 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.522 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.522 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.556 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.557 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.557 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.593 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.593 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.593 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.628 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.628 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.628 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.664 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.664 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.665 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.665 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.665 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.665 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.665 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.665 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.665 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.665 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.665 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.665 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.666 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.666 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.666 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.666 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.666 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.666 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.666 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.666 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.666 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.666 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.666 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.667 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.667 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.667 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:49.667 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.145 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.145 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.183 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.183 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.183 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.219 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.221 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.221 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.244 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.244 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.244 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.293 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.293 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.293 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.328 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.328 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.331 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.363 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.363 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.363 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.401 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.401 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.401 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.436 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.437 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.437 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.472 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.472 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.472 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.507 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.509 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.510 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.544 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.547 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.547 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.582 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.585 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.585 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.618 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.619 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.619 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.619 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.620 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.620 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.620 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.620 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.620 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.620 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.620 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.620 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.620 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.620 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.620 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.620 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.620 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.621 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.621 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.621 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.621 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.979 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:50.979 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.021 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.021 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.022 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.056 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.058 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.058 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.094 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.096 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.096 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.131 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.133 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.134 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.162 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.162 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.162 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.197 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.197 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.197 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.242 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.242 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.242 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.277 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.277 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.277 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.312 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.313 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.313 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.346 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.346 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.346 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.384 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.384 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.384 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:34:51.420 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:42.307 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:42.307 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:42.324 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:42.325 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:42.325 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:42.343 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:42.611 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:42.611 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:45.442 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:45.442 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:45.460 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:45.460 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:45.461 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:45.477 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:46.637 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:46.637 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:46.711 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:46.712 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:46.712 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:46.732 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:46.828 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:46.828 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:47.829 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:47.830 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:53.621 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:53.621 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:53.641 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:53.641 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:53.641 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:53.661 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:54.860 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:54.860 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:56.631 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:56.632 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:56.653 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:56.655 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:56.655 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:56.677 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:57.515 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:36:57.515 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:02.220 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:02.221 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:05.808 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:05.808 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:05.809 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:05.828 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.483 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 6073
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.483 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.483 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.533 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.533 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.533 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.534 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.534 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.534 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.534 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.534 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.534 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.534 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.534 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.535 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.535 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.535 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.535 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.535 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.535 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.535 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.535 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.535 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.535 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.535 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.535 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.535 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.535 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.536 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:09.536 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.003 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.003 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.003 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.003 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.003 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.003 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.003 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.003 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.003 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.004 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.004 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.004 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.004 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.004 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.004 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.004 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.004 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.004 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.004 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.004 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.363 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.363 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.398 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.399 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.399 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.434 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.435 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.435 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.469 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.469 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.469 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.504 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.506 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.507 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.541 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.543 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.543 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.582 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.582 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.582 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.617 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.617 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.617 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.617 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.618 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.618 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.618 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.618 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.618 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.618 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.618 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.618 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.618 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.618 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.618 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.619 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.619 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.619 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.619 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.619 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.619 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.619 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.620 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.620 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.620 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.620 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.620 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.638 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:10.638 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.090 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.091 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.126 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.126 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.126 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.161 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.161 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.161 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.196 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.198 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.198 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.233 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.233 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.234 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.269 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.269 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.269 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.304 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.306 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.307 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.343 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.343 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.343 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.378 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.378 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.378 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.412 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.413 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.413 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.448 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.450 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.450 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.451 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.451 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.452 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.452 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.453 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.453 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.453 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.453 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.453 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.453 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.453 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.453 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.453 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.453 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.453 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.454 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.454 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.454 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.454 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.454 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.454 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.454 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.454 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:11.454 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.145 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.145 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.179 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.180 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.180 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.214 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.215 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.215 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.249 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.250 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.250 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.285 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.285 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.285 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.320 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.320 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.321 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.355 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.359 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.360 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.394 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.394 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.394 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.429 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.429 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.429 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.464 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.466 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.467 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.502 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.503 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.503 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.538 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.538 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.539 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.574 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.574 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.575 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.609 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.609 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.609 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.609 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.609 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.610 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.610 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.610 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.610 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.610 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.610 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.610 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.610 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.610 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.610 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.610 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.610 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.610 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.611 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.611 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.611 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.970 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:12.971 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.006 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.006 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.007 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.041 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.041 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.041 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.076 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.076 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.076 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.111 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.112 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.113 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.149 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.150 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.151 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.185 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.185 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.186 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.221 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.221 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.222 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.256 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.257 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.257 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.293 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.293 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.293 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.328 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.328 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.328 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.363 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.364 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.365 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:13.400 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:15.405 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:15.405 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:15.646 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:15.646 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:15.646 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:15.663 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:15.663 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:15.663 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:15.679 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:15.679 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:15.679 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:15.681 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:15.681 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:15.757 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:15.918 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:15.918 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:15.918 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:15.936 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:17.368 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:17.369 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:27.208 DEBUG 948 [http-nio-8885-exec-11] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:27.208 DEBUG 948 [http-nio-8885-exec-11] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:27.225 DEBUG 948 [http-nio-8885-exec-11] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:27.226 DEBUG 948 [http-nio-8885-exec-11] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:27.226 DEBUG 948 [http-nio-8885-exec-11] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:27.241 DEBUG 948 [http-nio-8885-exec-11] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:27.242 DEBUG 948 [http-nio-8885-exec-11] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:27.242 DEBUG 948 [http-nio-8885-exec-11] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:27.259 DEBUG 948 [http-nio-8885-exec-11] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:27.260 DEBUG 948 [http-nio-8885-exec-11] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:27.260 DEBUG 948 [http-nio-8885-exec-11] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:27.276 DEBUG 948 [http-nio-8885-exec-11] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:27.291 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:27.291 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:27.309 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:27.309 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:27.309 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:28.975 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:29.951 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:29.951 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.434 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 6073
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.434 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.434 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.483 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.978 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.979 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.979 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.979 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.979 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.979 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.979 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.979 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.979 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.979 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.979 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.979 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.979 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.979 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.980 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.980 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.980 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.980 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.980 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:42.980 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.352 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.352 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.389 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.390 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.390 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.426 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.426 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.426 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.462 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.462 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.463 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.499 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.500 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.500 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.535 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.536 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.536 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.572 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.572 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.573 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.609 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.610 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.610 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.610 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.610 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.610 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.610 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.610 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.610 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.610 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.611 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.611 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.611 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.611 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.611 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.611 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.611 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.611 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.611 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.611 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.611 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.611 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.611 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.612 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.612 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.612 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:43.612 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.084 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.084 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.122 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.122 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.122 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.168 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.170 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.170 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.206 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.206 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.206 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.243 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.243 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.243 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.280 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.282 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.282 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.317 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.318 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.318 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.354 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.357 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.357 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.386 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.386 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.386 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.429 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.429 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.429 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.466 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.468 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.469 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.971 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:44.971 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.003 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.003 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.003 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.044 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.044 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.044 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.080 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.081 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.082 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.118 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.118 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.119 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.155 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.156 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.156 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.192 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.193 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.193 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.229 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.229 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.230 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.266 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.266 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.267 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.303 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.304 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.304 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.340 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.342 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.342 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.379 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.381 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.381 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.419 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.419 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.420 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.455 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.456 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.456 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.456 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.456 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.456 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.456 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.456 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.456 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.457 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.457 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.457 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.457 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.457 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.457 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.457 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.457 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.457 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.457 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.457 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.457 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.833 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.833 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.870 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.871 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.871 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.907 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.907 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.908 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.944 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.944 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.944 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.980 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.981 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:45.981 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.006 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.006 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.006 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.055 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.056 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.056 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.087 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.087 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.087 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.129 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.129 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.129 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.165 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.165 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.166 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.202 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.204 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.205 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.241 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.243 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.243 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:46.279 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 6082
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.196 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.196 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.248 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.248 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.249 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.249 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.249 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.249 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.249 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.249 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.249 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.249 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.249 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.249 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.249 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.250 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.250 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.250 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.250 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.250 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.250 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.250 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.250 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.250 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.250 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.250 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.251 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.251 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.251 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.786 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.786 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.787 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.788 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.788 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.788 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.788 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:53.788 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.203 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.203 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.203 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 6073
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.203 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.203 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.244 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.244 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.244 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.251 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.251 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.252 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.252 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.252 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.252 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.252 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.252 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.252 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.252 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.252 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.252 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.252 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.252 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.252 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.253 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.253 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.253 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.253 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.253 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.253 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.253 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.253 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.253 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.253 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.253 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.253 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.280 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.280 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.280 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.327 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.327 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.327 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.362 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.362 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.362 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.410 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.412 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.412 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.446 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.446 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.446 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.495 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.495 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.495 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.495 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.495 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.495 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.495 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.495 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.495 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.495 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.495 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.496 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.496 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.496 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.496 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.496 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.496 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.496 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.496 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.496 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.496 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.496 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.496 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.496 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.497 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.497 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.497 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.698 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.698 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.699 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.699 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.699 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.699 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.699 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.699 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.699 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.699 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.699 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.699 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.699 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.699 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.700 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.700 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.700 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.700 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.700 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:54.700 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.030 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.030 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.042 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.042 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.070 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.070 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.070 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.075 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.076 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.077 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.111 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.111 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.111 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.111 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.111 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.111 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.143 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.144 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.144 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.150 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.151 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.151 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.177 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.177 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.178 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.191 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.192 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.192 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.211 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.211 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.211 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.232 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.232 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.232 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.244 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.245 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.245 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.273 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.273 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.273 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.278 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.278 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.278 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.279 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.279 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.279 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.279 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.279 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.279 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.279 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.279 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.279 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.279 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.279 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.280 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.280 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.280 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.280 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.280 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.280 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.280 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.280 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.280 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.280 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.280 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.281 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.281 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.313 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.314 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.314 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.353 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.394 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.394 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.395 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.435 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.435 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.435 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.436 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.436 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.436 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.436 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.436 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.436 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.436 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.436 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.436 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.436 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.436 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.436 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.436 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.437 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.437 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.437 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.437 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.437 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.437 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.437 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.437 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.437 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.437 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.437 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.724 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.724 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.757 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.758 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.758 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.791 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.792 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.792 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.824 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.824 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.824 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.858 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.858 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.858 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.891 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.891 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.892 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.925 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.925 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.926 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.959 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.959 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.959 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.970 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.971 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.993 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.993 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:55.993 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.011 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.011 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.011 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.026 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.026 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.026 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.046 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.046 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.046 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.046 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.046 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.046 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.046 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.046 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.046 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.046 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.046 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.046 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.046 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.046 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.046 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.062 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.062 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.062 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.062 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.062 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.062 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.063 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.063 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.063 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.063 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.063 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.063 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.063 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.063 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.063 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.092 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.092 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.092 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.133 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.133 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.133 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.163 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.163 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.163 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.202 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.202 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.202 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.254 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.255 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.255 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.283 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.283 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.283 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.335 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.335 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.335 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.375 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.375 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.376 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.419 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.419 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.419 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.460 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.460 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.460 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.501 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.501 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.502 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.502 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.502 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.502 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.502 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.502 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.502 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.502 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.502 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.502 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.502 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.502 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.503 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.503 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.503 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.503 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.503 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.503 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.503 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.513 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.513 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.546 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.546 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.546 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.579 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.580 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.580 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.598 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.614 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.614 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.649 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.649 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.650 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.683 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.683 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.683 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.716 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.716 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.716 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.749 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.750 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.750 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.786 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.786 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.786 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.820 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.820 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.820 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.853 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.853 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.853 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.883 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.912 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.912 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.920 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.920 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.920 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.948 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.992 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.993 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:56.993 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.032 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.033 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.033 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.073 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.074 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.074 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.114 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.115 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.115 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.154 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.155 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.155 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.235 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.236 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.236 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.275 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.276 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.276 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.295 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.296 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.315 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.316 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.316 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.328 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.329 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.329 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.356 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.356 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.357 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.362 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.362 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.362 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.396 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.396 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.396 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.397 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.430 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.430 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.430 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.463 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.463 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.464 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.497 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.498 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.498 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.530 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.531 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.531 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.565 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.567 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.567 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.601 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.602 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.602 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.635 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.635 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.636 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.669 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.669 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.669 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.702 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.751 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 6073
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.752 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.752 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.806 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 83
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.806 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.807 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.807 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.807 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.807 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.807 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.807 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.807 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.807 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.807 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.807 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.807 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.807 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.807 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.808 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.808 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.808 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.808 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.808 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.808 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.808 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.808 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.808 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.808 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.808 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:57.808 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.352 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.352 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.352 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.352 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.352 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.352 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.352 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.352 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.352 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.353 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.353 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.353 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.353 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.353 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.353 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.353 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.353 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.353 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.353 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.353 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.771 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.772 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.813 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.813 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.813 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.858 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.858 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.858 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.899 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.899 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.900 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.940 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.942 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.943 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.984 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.985 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:58.985 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.025 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.025 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.025 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.067 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.068 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.068 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.068 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.068 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.068 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.068 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.068 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.068 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.068 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.068 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.068 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.069 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.069 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.069 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.069 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.069 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.069 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.069 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.069 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.069 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.069 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.069 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.069 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.069 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.070 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.070 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.620 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.620 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.660 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.660 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.662 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.701 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.702 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.702 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.743 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.743 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.743 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.784 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.786 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.786 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.826 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.826 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.826 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.868 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.868 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.868 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.908 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.909 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.909 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.950 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.952 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.953 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.995 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.997 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:37:59.997 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.037 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.038 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.038 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.038 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.038 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.038 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.039 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.039 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.039 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.039 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.039 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.039 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.039 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.039 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.039 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.039 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.039 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.039 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.039 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.040 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.040 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.040 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.040 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.040 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.040 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.040 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.040 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.586 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.586 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.627 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.627 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.628 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.668 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.669 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.670 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.710 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.710 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.710 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.751 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.754 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.754 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.794 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.795 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.796 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.836 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.836 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.837 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.877 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.878 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.878 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.918 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.919 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.919 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.961 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.961 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:00.961 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.001 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.002 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.002 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.037 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.037 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.037 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.084 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.085 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.085 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.126 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.126 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.127 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.127 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.127 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.127 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.127 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.127 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.127 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.127 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.127 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.127 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.127 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.127 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.127 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.128 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.128 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.128 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.128 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.128 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.128 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.578 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.579 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.620 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.621 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.621 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.662 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.662 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.662 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.702 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.703 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.703 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.744 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.744 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.745 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.785 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.786 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.787 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.828 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.828 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.829 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.869 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.870 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.870 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.911 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.912 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.912 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.952 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.953 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.954 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.987 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.987 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:01.987 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.035 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.036 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.036 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.076 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.343 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 6186
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.344 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.344 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.391 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.392 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.392 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.392 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.393 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.393 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.393 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.393 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.393 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.393 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.393 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.393 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.393 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.393 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.393 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.393 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.393 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.393 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.394 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.394 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.394 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.394 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.394 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.394 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.394 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.394 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.394 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.859 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.859 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.859 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.859 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.859 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.859 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.860 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.860 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.860 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.860 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.860 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.860 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.860 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.860 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.860 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.860 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.860 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.860 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.860 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:02.861 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.222 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.222 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.263 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.263 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.263 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.311 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.311 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.311 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.360 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.362 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.362 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.405 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.406 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.406 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.446 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.446 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.446 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.483 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.483 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.483 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.528 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.529 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.529 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.529 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.529 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.530 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.530 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.530 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.530 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.530 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.530 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.530 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.530 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.530 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.530 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.530 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.530 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.530 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.531 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.531 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.531 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.531 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.531 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.531 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.531 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.531 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:03.531 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.141 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.142 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.188 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.189 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.189 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.229 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.229 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.229 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.270 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.271 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.271 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.306 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.306 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.306 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.342 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.342 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.343 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.379 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.381 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.381 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.407 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.407 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.407 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.452 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.452 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.452 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.490 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.491 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.491 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.523 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.990 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:04.990 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.031 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.032 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.032 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.066 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.068 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.068 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.104 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.106 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.107 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.142 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.145 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.145 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.180 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.180 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.180 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.214 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.215 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.216 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.251 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.251 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.251 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.286 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.286 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.286 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.321 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.321 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.321 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.356 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.358 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.359 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.393 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.393 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.394 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.429 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.430 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.430 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.464 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.464 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.465 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.465 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.465 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.465 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.465 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.465 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.465 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.465 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.465 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.465 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.465 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.466 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.466 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.466 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.466 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.466 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.466 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.466 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.466 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.830 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.831 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.864 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.865 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.865 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.899 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.900 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.900 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.935 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.935 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.935 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.972 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.972 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:05.973 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.007 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.007 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.007 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.043 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.043 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.044 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.078 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.078 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.078 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.107 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.107 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.107 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.149 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.149 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.149 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.184 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.184 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.185 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.219 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.219 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.219 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:06.241 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:07.980 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 6186
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:07.981 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:07.981 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.029 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.030 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.030 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.030 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.030 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.509 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.509 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.510 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.510 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.510 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.510 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.510 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.510 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.510 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.510 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.510 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.510 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.510 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.510 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.511 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.511 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.511 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.511 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.511 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.511 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.880 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.880 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.917 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.917 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.917 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.952 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.953 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.953 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.989 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.990 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:08.990 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.025 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.025 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.025 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.061 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.061 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.061 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.083 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.083 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.083 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.133 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.134 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.134 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.134 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.134 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.135 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.135 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.135 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.135 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.135 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.135 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.135 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.136 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.136 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.136 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.151 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.151 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.151 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.151 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.151 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.151 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.152 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.152 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.152 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.152 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.152 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.152 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.637 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.637 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.638 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 6073
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.639 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.639 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.673 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.673 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.673 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.689 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.689 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.689 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.690 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.690 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.690 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.690 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.690 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.690 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.690 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.690 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.690 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.690 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.690 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.690 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.691 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.691 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.691 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.691 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.691 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.691 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.691 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.691 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.691 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.691 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.691 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.691 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.709 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.709 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.710 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.743 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.743 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.745 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.780 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.780 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.781 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.816 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.816 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.817 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.844 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.844 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.844 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.887 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.887 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.887 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.922 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.923 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.923 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.959 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.959 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.959 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.994 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.995 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.995 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.996 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.996 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.996 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.996 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.996 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.996 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.996 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.996 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.996 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.996 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.996 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.996 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.997 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.997 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.997 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.997 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.997 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.997 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.997 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.997 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.997 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.997 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.997 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:09.997 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.202 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.204 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.204 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.204 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.204 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.204 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.204 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.475 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.475 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.511 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.512 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.512 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.547 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.547 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.548 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.582 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.583 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.583 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.602 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.602 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.618 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.618 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.618 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.642 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.642 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.642 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.654 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.655 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.655 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.680 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.681 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.681 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.690 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.691 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.691 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.720 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.720 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.720 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.727 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.727 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.727 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.759 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.759 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.760 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.762 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.763 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.763 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.799 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.799 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.800 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.802 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.802 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.802 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.837 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.837 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.837 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.840 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.840 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.840 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.873 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.873 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.874 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.874 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.874 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.874 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.874 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.874 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.874 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.874 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.874 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.874 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.874 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.874 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.875 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.875 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.875 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.875 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.875 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.875 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.875 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.875 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.875 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.875 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.875 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.875 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.875 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.878 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.879 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.879 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.918 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.918 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.919 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.957 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.958 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.958 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.958 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.958 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.958 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.958 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.958 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.958 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.958 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.959 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.959 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.959 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.959 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.959 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.959 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.959 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.959 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.959 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.959 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:10.959 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.350 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.351 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.358 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.358 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.387 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.387 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.387 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.397 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.397 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.397 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.423 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.423 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.424 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.436 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.437 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.437 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.459 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.459 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.459 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.475 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.475 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.475 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.494 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.495 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.495 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.514 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.514 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.514 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.530 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.533 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.534 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.554 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.554 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.554 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.614 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.615 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.615 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.634 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.635 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.635 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.650 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.651 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.651 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.672 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.673 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.673 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.687 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.687 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.687 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.711 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.712 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.713 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.722 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.722 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.723 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.756 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.756 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.756 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.762 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.763 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.764 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.764 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.764 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.764 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.764 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.764 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.764 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.764 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.764 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.764 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.764 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.764 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.764 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.765 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.765 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.765 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.765 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.765 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.765 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.765 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.765 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.765 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.765 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.765 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.765 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.795 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.795 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.795 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.834 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.835 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.835 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:11.873 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.241 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.241 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.277 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.277 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.278 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.313 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.314 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.314 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.349 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.350 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.350 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.385 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.385 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.386 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.421 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.421 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.422 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.457 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.457 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.457 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.493 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.493 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.494 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.530 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.532 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.533 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.568 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.568 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.569 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.604 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.604 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.605 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.641 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.641 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.641 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.677 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.677 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.678 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.713 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.713 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.714 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.714 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.714 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.714 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.714 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.714 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.714 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.714 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.714 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.715 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.715 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.715 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.715 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.715 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.715 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.715 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.715 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.715 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:12.715 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.082 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.082 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.118 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.118 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.118 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.154 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.154 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.154 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.190 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.191 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.191 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.226 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.227 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.227 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.265 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.265 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.266 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.301 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.302 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.302 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.338 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.338 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.338 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.374 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.375 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.375 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.411 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.411 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.412 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.447 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.447 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.448 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.483 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.483 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.484 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:38:13.518 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:02.049 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:02.049 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:02.066 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:02.066 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:02.067 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:02.073 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:02.440 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:02.440 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:03.398 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:03.399 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:03.417 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:03.417 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:03.418 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:03.437 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:04.231 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:04.231 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:08.683 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:08.684 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:08.701 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:08.701 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:08.701 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:08.719 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:10.572 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:10.572 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.603 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 7011
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.603 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.603 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.654 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 76
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.655 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.655 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.655 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.655 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.655 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.655 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.655 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.656 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.656 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.656 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.656 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.656 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.656 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.656 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.656 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.656 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.656 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.656 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.656 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.656 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.657 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.657 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.657 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.657 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.657 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:27.657 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.135 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.135 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.135 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.135 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.135 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.135 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.135 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.135 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.135 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.136 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.136 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.136 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.136 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.136 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.136 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.136 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.136 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.136 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.136 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.136 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.502 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.503 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.539 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.541 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.541 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.577 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.577 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.577 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.613 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.614 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.614 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.649 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.650 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.650 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.686 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.688 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.688 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.723 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.724 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.724 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.761 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.761 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.762 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.762 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.762 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.762 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.762 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.762 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.762 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.762 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.762 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.762 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.762 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.762 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.763 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.763 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.763 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.763 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.763 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.763 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.763 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.763 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.763 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.763 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.763 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.763 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:28.763 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.242 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.242 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.278 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.279 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.279 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.315 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.315 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.315 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.351 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.351 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.352 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.387 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.387 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.387 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.423 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.423 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.424 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.458 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.459 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.459 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.494 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.495 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.495 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.531 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.531 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.532 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.567 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.567 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.568 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.603 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.604 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.604 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.604 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.604 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.604 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.604 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.604 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.604 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.604 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.604 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.605 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.605 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.605 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.605 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.605 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.605 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.605 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.605 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.605 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.605 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.605 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.605 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.605 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.605 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.606 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:29.606 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.068 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.068 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.104 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 7011
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.105 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.105 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.106 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.106 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.106 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.153 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.154 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.154 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.156 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 19
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.156 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.156 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.156 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.157 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.157 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.157 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.157 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.157 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.157 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.157 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.157 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.157 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.157 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.157 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.157 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.158 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.158 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.158 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.158 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.158 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.158 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.158 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.158 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.158 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.158 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.158 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.189 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.191 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.191 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.227 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.227 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.228 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.263 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.265 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.266 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.301 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.302 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.302 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.322 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.338 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.338 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.373 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.375 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.376 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.411 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.411 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.411 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.437 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.437 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.437 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.482 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.483 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.483 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.518 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.519 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.519 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.555 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.555 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.556 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.556 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.556 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.556 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.556 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.556 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.556 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.556 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.556 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.556 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.556 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.556 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.557 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.557 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.557 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.557 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.557 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.557 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.557 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.676 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.677 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.677 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.678 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.678 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.678 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.679 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.679 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.680 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.680 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.680 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.681 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.682 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.682 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.682 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.683 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.683 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.684 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.684 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.684 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.927 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.927 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.952 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.952 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:30.952 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.000 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.000 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.001 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.034 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.036 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.036 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.071 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.073 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.074 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.110 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.110 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.110 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.145 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.146 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.146 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.182 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.182 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.183 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.217 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.217 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.218 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.254 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.254 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.255 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.290 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.290 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.291 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.307 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.307 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.325 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.325 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.326 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.346 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.347 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.347 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.361 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.388 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.388 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.389 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.427 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.427 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.427 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.466 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.467 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.468 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.506 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.507 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.507 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.546 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.546 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.547 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.585 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.587 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.587 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.587 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.587 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.587 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.587 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.587 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.587 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.587 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.587 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.587 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.587 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.588 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.588 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.588 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.588 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.588 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.588 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.588 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.588 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.588 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.588 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.588 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.588 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.588 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:31.589 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.109 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.109 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.148 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.149 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.149 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.187 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.187 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.188 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.227 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.227 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.227 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.265 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.266 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.267 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.306 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.307 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.307 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.345 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.345 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.346 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.385 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.385 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.386 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.424 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.426 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.427 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.466 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.466 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.467 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.505 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.506 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.506 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.506 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.506 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.506 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.506 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.506 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.506 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.506 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.507 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.507 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.507 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.507 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.507 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.507 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.507 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.507 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.507 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.507 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.507 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.507 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.507 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.507 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.508 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.508 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:32.508 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.032 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.033 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.072 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.072 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.072 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.111 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.111 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.112 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.150 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.151 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.151 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.190 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.191 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.191 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.230 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.232 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.232 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.271 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.273 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.274 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.312 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.312 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.313 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.352 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.352 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.353 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.392 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.394 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.394 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.432 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.433 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.433 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.472 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.473 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.473 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.512 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.512 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.513 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.552 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.552 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.553 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.553 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.553 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.553 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.553 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.553 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.553 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.553 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.553 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.553 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.553 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.554 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.554 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.554 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.554 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.554 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.554 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.554 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.554 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.955 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.956 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.994 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.995 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:33.995 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.034 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.036 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.036 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.075 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.076 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.076 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.114 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.115 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.115 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.153 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.154 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.154 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.189 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.189 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.189 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.233 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.235 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.235 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.274 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.274 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.275 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.314 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.315 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.315 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.354 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.354 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.355 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.389 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.389 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.389 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:34.433 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.876 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 7011
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.877 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.877 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 65
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:36.925 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.395 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.396 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.396 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.396 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.396 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.396 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.396 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.396 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.396 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.396 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.397 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.397 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.397 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.397 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.397 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.397 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.397 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.397 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.397 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.397 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.758 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.759 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.794 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.796 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.796 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.831 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.831 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.832 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.866 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.866 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.867 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.902 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.902 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.903 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.937 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.937 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.938 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.972 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.972 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:37.973 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.007 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.008 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.008 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.008 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.008 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.008 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.008 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.008 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.008 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.008 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.008 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.009 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.009 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.009 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.009 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.009 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.009 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.009 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.009 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.010 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.010 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.010 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.010 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.010 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.010 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.010 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.010 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.485 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.486 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.520 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.520 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.521 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.556 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.556 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.557 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.591 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.592 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.592 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.627 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.628 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.628 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.662 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.664 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.664 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.700 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.702 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.703 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.738 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.738 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.739 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.773 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.775 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.775 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.811 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.812 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.812 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.847 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.848 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.848 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.848 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.848 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.848 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.848 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.848 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.848 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.848 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.849 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.849 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.849 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.849 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.849 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.849 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.849 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.849 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.849 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.849 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.850 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.850 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.850 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.850 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.850 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.850 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:38.850 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.318 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.318 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.353 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.354 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.355 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.390 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.391 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.391 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.426 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.427 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.427 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.462 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.463 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.463 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.497 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.497 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.498 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.533 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.535 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.536 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.571 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.573 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.574 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.610 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.611 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.612 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.647 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.649 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.650 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.685 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.687 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.687 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.722 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.724 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.724 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.760 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.761 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.761 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.797 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.797 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.797 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.797 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.797 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.797 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.797 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.797 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.797 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.798 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.798 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.798 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.798 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.798 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.798 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.798 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.798 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.798 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.798 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.798 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:39.798 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.158 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.159 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.193 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.195 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.196 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.231 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.233 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.233 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.268 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.268 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.269 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.303 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.303 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.304 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.338 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.338 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.339 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.373 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.374 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.374 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.409 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.409 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.410 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.445 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.447 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.483 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.484 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.484 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.518 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.518 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.519 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.553 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.554 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.554 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:40:40.589 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:22.719 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:22.720 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:22.737 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:22.737 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:22.738 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:22.754 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:23.138 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:23.139 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:25.040 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:25.041 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:25.061 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:25.062 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:25.063 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:25.083 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:25.866 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:25.867 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:34.722 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:34.722 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:34.804 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:34.804 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:34.804 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:34.822 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:35.735 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:35.735 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:37.402 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:37.402 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:37.429 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:37.430 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:37.430 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:37.450 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.471 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 7316
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.471 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.472 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.519 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.520 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.520 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.520 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.520 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.521 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.521 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.521 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.521 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.521 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.521 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.521 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.521 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.521 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.521 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.521 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.521 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.522 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.522 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.522 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.522 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.522 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.522 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.522 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.522 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.522 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.522 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.988 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.989 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.989 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.989 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.989 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.989 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.989 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.989 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.989 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.989 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.989 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.989 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.989 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.989 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.990 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.990 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.990 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.990 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.990 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:38.990 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.349 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.350 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.384 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.385 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.385 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.419 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.420 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.420 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.455 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.455 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.456 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.491 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.493 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.493 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.528 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.530 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.531 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.566 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.567 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.567 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.601 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.602 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.602 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.602 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.602 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.602 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.602 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.602 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.602 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.602 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.602 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.603 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.603 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.603 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.603 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.603 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.603 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.603 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.603 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.603 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.603 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.603 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.603 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.603 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.604 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.604 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:39.604 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.067 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.069 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.088 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.104 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.104 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.138 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.139 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.139 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.174 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.174 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.175 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.204 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.204 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.204 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.247 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.249 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.249 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.272 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.272 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.272 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.320 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.322 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.323 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.355 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.355 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.355 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.393 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.393 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.394 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.429 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.429 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.430 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.430 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.430 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.430 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.430 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.430 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.430 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.430 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.430 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.430 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.430 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.430 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.430 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.431 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.431 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.431 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.431 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.431 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.431 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.431 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.431 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.431 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.431 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.431 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.431 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.533 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.533 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.553 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.553 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.553 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.574 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.888 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.888 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.931 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.931 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.932 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.967 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.967 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.968 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.989 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.989 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:40.989 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.037 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.040 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.040 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.076 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.076 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.077 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.111 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.111 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.112 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.147 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.147 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.148 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.182 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.183 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.183 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.218 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.219 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.220 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.254 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.254 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.255 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.289 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.290 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.291 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.326 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.326 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.327 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.361 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.364 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.365 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.365 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.365 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.366 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.366 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.367 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.367 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.368 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.368 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.368 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.369 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.369 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.369 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.370 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.370 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.371 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.371 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.371 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.371 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.735 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.735 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.768 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.769 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.769 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.804 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.805 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.805 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.839 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.841 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.841 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.875 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.876 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.876 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.911 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.912 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.912 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.946 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.947 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.947 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.982 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.982 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:41.982 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.018 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.018 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.019 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.053 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.055 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.056 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.090 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.093 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.094 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.132 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.134 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.135 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.170 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.213 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.213 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.584 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.585 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.606 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.608 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.608 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:42.629 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:43.124 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:43.124 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:45.133 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:45.134 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:45.305 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:45.306 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:45.326 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:45.326 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:45.326 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:45.345 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:46.591 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:41:46.591 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.716 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 7316
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.716 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.717 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.770 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.771 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.771 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.771 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.771 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.771 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.771 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.771 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.772 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.772 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.772 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.772 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.772 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.772 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.772 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.772 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.772 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.772 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.772 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.772 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.773 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.773 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.773 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.773 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.773 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.773 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:29.773 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.296 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.297 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.297 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.298 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.298 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.298 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.299 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.300 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.300 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.301 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.301 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.301 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.302 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.302 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.303 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.303 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.303 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.303 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.303 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.304 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.706 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.706 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.745 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.745 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.746 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.785 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.786 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.786 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.824 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.827 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.827 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.866 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.867 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.867 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.905 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.905 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.906 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.945 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.945 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.946 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.984 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.985 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.985 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.985 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.985 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.985 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.985 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.985 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.985 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.986 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.986 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.986 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.986 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.986 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.986 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.986 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.986 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.986 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.986 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.987 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.987 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.987 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.987 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.987 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.987 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.987 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:30.987 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.506 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.506 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.546 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.546 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.547 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.585 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.587 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.587 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.626 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.628 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.629 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.668 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.668 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.668 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.706 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.707 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.708 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.746 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.746 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.747 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.785 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.786 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.786 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.824 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.826 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.827 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.866 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.866 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.867 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.906 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.909 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.909 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.910 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.910 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.911 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.911 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.911 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.912 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.912 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.913 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.913 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.913 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.913 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.913 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.913 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.913 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.913 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.913 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.914 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.914 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.914 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.914 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.914 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.914 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.914 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:31.914 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.430 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.431 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.470 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.472 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.473 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.511 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.511 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.512 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.551 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.551 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.552 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.590 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.591 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.591 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.630 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.630 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.631 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.670 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.671 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.671 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.709 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.709 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.710 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.749 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.751 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.751 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.790 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.792 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.793 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.835 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.837 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.837 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.876 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.877 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.877 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.916 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.917 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.917 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.956 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.956 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.956 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.956 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.956 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.956 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.957 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.957 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.957 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.957 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.957 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.957 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.957 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.957 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.957 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.957 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.957 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.957 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.958 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.958 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:32.958 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.359 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.359 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.398 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.398 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.399 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.436 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.437 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.437 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.476 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.477 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.477 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.515 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.516 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.516 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.555 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.555 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.556 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.595 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.596 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.596 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.634 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.634 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.635 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.673 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.674 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.674 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.713 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.715 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.715 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.754 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.756 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.756 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.795 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.796 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.796 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:33.835 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.120 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 7429
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.121 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.121 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.167 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.167 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.168 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.168 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.168 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.168 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.168 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.168 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.168 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.168 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.168 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.168 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.169 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.169 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.169 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.169 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.169 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.169 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.169 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.169 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.169 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.169 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.169 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.170 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.170 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.170 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.170 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.615 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.615 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.615 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.615 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.615 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.615 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.615 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.615 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.615 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.615 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.615 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.616 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.616 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.616 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.616 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.616 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.616 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.616 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.616 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.617 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.958 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.959 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.992 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.992 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:37.993 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.026 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.027 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.027 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.060 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.063 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.063 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.097 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.097 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.098 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.130 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.132 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.133 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.167 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.167 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.168 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.200 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.201 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.202 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.202 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.202 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.202 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.202 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.202 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.202 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.202 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.202 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.202 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.202 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.203 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.204 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.204 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.204 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.301 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 7429
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.301 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.301 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.348 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.348 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.349 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.349 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.349 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.349 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.349 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.349 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.349 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.349 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.349 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.349 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.349 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.349 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.349 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.350 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.350 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.350 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.350 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.350 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.350 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.350 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.350 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.350 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.350 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.350 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.350 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.652 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.652 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.687 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.688 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.688 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.720 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.721 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.721 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.753 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.754 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.754 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.787 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.788 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.788 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.815 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.815 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.816 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.816 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.817 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.817 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.817 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.817 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.817 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.817 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.817 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.817 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.817 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.817 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.818 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.818 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.818 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.818 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.818 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.818 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.822 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.822 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.822 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.855 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.858 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.859 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.892 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.893 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.893 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.926 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.926 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.927 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.960 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.960 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.961 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.994 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.997 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.998 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.998 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.999 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:38.999 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.000 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.000 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.001 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.001 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.002 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.002 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.002 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.003 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.003 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.004 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.004 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.004 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.005 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.005 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.006 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.006 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.006 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.007 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.007 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.008 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.008 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.176 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.177 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.211 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.213 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.214 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.248 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.250 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.250 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.285 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.285 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.286 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.320 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.322 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.323 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.358 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.358 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.359 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.393 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.393 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.394 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.429 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.429 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.430 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.430 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.430 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.430 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.430 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.430 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.430 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.431 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.431 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.431 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.431 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.431 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.431 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.431 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.432 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.432 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.432 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.432 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.432 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.432 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.432 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.432 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.432 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.433 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.433 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.450 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.451 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.484 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.484 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.485 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.517 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.517 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.518 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.551 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.551 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.552 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.585 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.587 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.587 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.621 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.621 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.622 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.655 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.656 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.656 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.689 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.689 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.690 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.722 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.722 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.723 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.756 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.758 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.759 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.791 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.792 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.792 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.828 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.828 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.829 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.861 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.862 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.862 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.894 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.895 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.895 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.895 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.896 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.896 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.896 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.896 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.896 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.896 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.896 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.896 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.896 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.896 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.896 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.896 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.896 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.896 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.897 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.897 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.897 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.900 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.900 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.907 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 7429
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.908 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.908 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.934 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.935 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.935 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.962 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 31
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.962 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.963 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.963 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.963 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.963 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.963 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.963 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.963 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.963 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.963 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.963 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.963 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.964 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.964 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.964 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.964 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.964 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.964 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.964 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.964 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.964 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.964 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.964 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.964 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.964 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.965 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.970 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.972 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:39.972 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.007 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.009 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.010 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.044 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.046 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.046 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.081 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.082 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.082 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.117 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.117 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.118 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.152 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.153 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.154 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.188 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.188 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.189 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.223 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.223 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.224 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.242 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.243 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.259 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.261 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.262 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.262 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.263 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.263 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.264 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.264 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.264 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.265 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.265 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.266 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.266 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.266 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.267 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.267 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.268 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.268 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.268 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.269 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.269 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.269 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.269 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.270 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.270 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.270 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.270 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.276 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.276 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.277 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.309 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.309 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.309 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.343 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.344 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.344 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.376 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.376 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.377 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.410 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.413 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.414 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.447 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.447 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.448 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.480 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.481 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.481 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.510 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.511 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.511 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.512 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.512 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.513 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.513 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.513 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.513 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.513 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.513 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.513 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.513 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.513 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.513 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.513 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.514 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.514 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.514 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.514 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.514 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.515 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.515 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.548 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.549 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.549 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.582 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.582 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.583 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.616 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.618 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.618 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.652 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.734 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.735 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.769 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.769 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.770 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.804 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.805 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.805 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.840 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.841 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.841 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.875 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.876 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.876 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.910 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.910 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.910 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.931 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.931 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.945 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.945 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.945 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.972 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.973 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.973 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.980 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.981 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:40.981 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.014 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.014 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.015 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.015 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.015 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.016 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.050 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.051 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.051 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.055 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.058 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.058 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.082 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.082 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.082 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.098 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.101 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.102 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.124 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.124 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.124 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.143 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.143 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.144 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.149 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.149 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.149 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.184 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.186 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.186 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.195 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.195 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.195 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.195 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.195 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.196 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.196 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.196 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.196 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.196 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.196 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.196 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.196 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.196 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.196 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.196 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.196 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.196 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.197 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.197 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.197 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.197 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.197 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.197 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.197 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.197 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.197 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.227 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.228 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.228 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.228 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.228 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.228 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.228 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.228 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.228 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.228 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.228 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.228 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.228 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.228 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.229 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.229 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.229 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.229 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.229 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.229 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.229 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.647 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.647 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.662 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.662 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.688 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.691 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.691 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.697 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.699 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.700 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.732 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.733 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.735 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.735 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.736 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.737 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.771 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.772 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.773 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.778 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.778 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.778 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.807 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.807 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.808 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.819 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.819 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.820 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.842 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.843 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.843 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.861 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.861 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.862 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.877 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.879 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.880 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.902 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.902 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.903 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.914 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.916 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.916 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.943 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.944 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.944 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.950 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.951 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.951 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.985 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.985 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.985 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.985 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.986 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:41.986 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.020 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.022 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.023 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.026 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.028 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.029 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.058 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.060 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.061 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.069 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.072 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.073 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.073 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.073 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.074 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.074 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.075 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.075 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.076 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.076 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.077 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.077 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.077 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.078 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.078 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.079 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.079 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.079 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.080 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.080 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.081 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.081 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.081 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.081 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.082 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.082 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.096 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.632 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.633 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.678 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.680 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.680 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.722 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.723 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.723 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.763 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.765 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.765 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.806 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.809 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.809 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.850 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.851 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.851 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.892 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.892 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.892 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.934 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.935 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.935 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.976 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.976 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:42.977 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.016 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.018 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.018 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.058 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.059 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.059 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.100 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.100 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.102 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.142 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.143 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.143 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.185 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.612 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.612 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.654 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.654 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.655 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.684 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.684 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.684 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.739 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.739 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.740 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.781 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.782 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.782 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.823 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.824 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.825 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.865 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.867 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.868 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.910 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.910 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.911 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.951 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.953 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.954 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.985 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.985 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:43.985 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:44.037 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:44.038 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:44.039 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:44.081 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:44.082 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:44.082 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:44.122 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.218 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 7429
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.219 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.219 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.274 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 88
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.275 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.275 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.275 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.275 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.275 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.275 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.275 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.275 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.275 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.275 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.275 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.276 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.276 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.276 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.276 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.276 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.276 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.276 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.276 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.276 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.276 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.276 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.276 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.276 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.277 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.277 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.815 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.815 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.815 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.815 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.816 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.816 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.816 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.816 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.816 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.816 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.816 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.816 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.816 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.816 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.816 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.816 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.816 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.817 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.817 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:56.817 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.231 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.231 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.271 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.271 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.272 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.313 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.314 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.315 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.355 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.357 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.358 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.397 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.399 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.399 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.439 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.439 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.440 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.479 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.481 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.481 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.521 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.522 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.522 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.522 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.522 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.522 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.522 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.522 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.522 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.522 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.523 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.523 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.523 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.523 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.523 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.523 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.523 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.523 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.523 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.523 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.523 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.523 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.524 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.524 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.524 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.524 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:57.524 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.061 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.061 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.101 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.102 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.103 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.142 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.142 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.143 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.183 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.185 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.186 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.226 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.227 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.227 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.267 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.269 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.269 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.310 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.310 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.311 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.349 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.349 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.349 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.392 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.394 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.395 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.435 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.437 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.437 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.479 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.480 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.480 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.480 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.480 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.480 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.480 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.480 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.480 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.480 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.481 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.481 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.481 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.481 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.481 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.481 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.481 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.481 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.481 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.481 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.481 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.481 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.482 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.482 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.482 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.482 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:58.482 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.018 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.018 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.058 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.059 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.059 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.099 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.100 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.100 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.141 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.142 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.142 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.181 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.182 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.182 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.222 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.223 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.223 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.263 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.265 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.266 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.306 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.306 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.306 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.347 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.347 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.348 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.388 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.391 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.391 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.431 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.432 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.432 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.471 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.473 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.474 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.514 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.516 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.517 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.557 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.558 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.558 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.558 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.558 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.558 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.558 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.558 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.558 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.558 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.558 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.559 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.559 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.559 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.559 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.559 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.559 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.559 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.559 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.559 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.559 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.973 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:42:59.973 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.013 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.014 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.014 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.055 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.055 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.056 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.096 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.096 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.097 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.137 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.138 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.138 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.178 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.178 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.179 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.219 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.220 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.220 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.260 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.262 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.263 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.302 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.306 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.306 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.346 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.348 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.349 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.390 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.392 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.392 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.434 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.436 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.437 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:00.476 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 7316
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.471 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.509 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.525 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.525 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.525 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.525 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.525 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:08.525 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.002 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.002 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.002 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.002 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.002 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.002 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.002 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.002 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.002 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.002 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.002 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.003 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.003 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.003 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.003 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.003 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.003 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.003 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.003 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.003 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.370 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.371 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.407 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.407 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.408 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.443 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.444 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.444 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.480 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.481 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.481 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.516 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.518 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.519 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.555 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.555 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.556 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.590 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.590 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.591 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.626 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.627 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.627 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.627 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.627 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.627 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.627 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.627 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.627 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.627 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.627 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.628 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.628 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.628 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.628 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.628 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.628 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.628 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.628 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.628 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.628 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.628 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.628 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.629 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.629 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.629 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:09.629 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.107 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.108 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.144 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.146 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.147 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.182 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.184 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.184 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.220 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.220 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.221 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.256 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.257 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.257 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.292 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.293 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.293 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.329 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.330 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.330 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.366 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.368 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.368 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.404 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.404 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.405 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.440 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.440 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.441 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.476 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.477 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.478 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.478 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.478 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.478 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.478 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.478 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.478 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.478 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.478 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.479 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.479 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.479 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.479 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.479 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.479 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.479 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.479 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.479 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.479 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.479 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.479 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.479 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.480 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.480 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.480 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.953 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.953 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.988 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.989 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:10.989 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.024 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.025 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.025 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.060 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.062 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.062 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.098 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.099 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.099 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.134 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.134 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.135 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.162 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.162 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.162 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.206 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.206 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.207 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.229 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.229 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.229 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.280 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.280 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.280 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.318 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.320 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.320 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.357 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.358 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.359 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.395 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.396 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.396 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.429 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.795 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.795 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.829 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.829 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.829 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.866 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.867 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.867 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.902 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.903 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.903 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.938 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.939 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.939 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.963 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.963 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:11.963 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:12.009 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:12.011 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:12.011 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:12.046 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:12.047 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:12.048 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:12.082 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:12.083 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:12.084 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:12.118 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:12.120 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:12.120 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:12.155 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:12.156 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:12.156 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:12.191 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:12.192 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:12.192 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:43:12.227 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:44:53.602 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:44:53.602 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:44:53.620 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:44:53.620 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:44:53.620 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:44:53.634 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:44:53.635 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:44:53.638 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:44:53.655 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:44:53.656 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:44:53.656 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:44:53.675 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:44:53.980 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:44:53.980 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:44:54.028 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:44:54.028 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:01.739 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:01.739 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:01.837 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:01.837 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:01.838 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:01.858 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:02.967 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:02.967 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:12.321 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:12.322 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:12.339 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:12.339 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:12.340 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:12.356 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:12.991 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:12.991 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:14.394 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:14.394 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:14.473 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:14.474 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:14.474 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:14.490 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:16.326 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:16.326 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.493 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 8107
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.494 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.494 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.542 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.545 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.545 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.546 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.546 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.546 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.546 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.546 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.546 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.546 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.546 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.546 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.547 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.547 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.547 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.547 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.547 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.547 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.547 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.547 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.547 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.547 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.547 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.548 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.548 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.548 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:38.548 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.023 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.024 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.024 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.024 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.024 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.024 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.024 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.024 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.024 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.024 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.024 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.024 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.025 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.025 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.025 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.025 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.025 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.025 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.025 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.025 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.607 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.607 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.643 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.643 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.643 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.678 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.679 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.679 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.715 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.715 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.716 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.751 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.753 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.753 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.789 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.791 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.792 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.827 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.828 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.828 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.864 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.865 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.865 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.865 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.865 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.865 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.865 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.865 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.866 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.866 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.866 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.866 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.866 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.866 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.866 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.866 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.866 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.866 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.866 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.866 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.866 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.867 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.867 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.867 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.867 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.867 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:39.867 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.344 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.345 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.379 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.381 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.381 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.416 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.416 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.417 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.444 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.444 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.444 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.490 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.490 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.491 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.511 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.527 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.527 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.563 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.564 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.564 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.600 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.600 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.601 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.636 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.636 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.636 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.673 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.674 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.674 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.709 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.711 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.711 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.711 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.711 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.711 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.711 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.711 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.711 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.711 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.712 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.712 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.712 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.712 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.712 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.712 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.712 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.712 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.712 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.712 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.713 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.713 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.713 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.713 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.713 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.713 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:40.713 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.404 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.404 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.440 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.441 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.441 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.476 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.477 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.477 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.533 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.535 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.536 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.571 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.574 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.574 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.610 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.610 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.611 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.646 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.647 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.647 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.682 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.682 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.683 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.719 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.721 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.722 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.757 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.759 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.760 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.794 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.796 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.796 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.831 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.832 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.832 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.867 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.868 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.868 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.904 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.906 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.907 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.908 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.908 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.909 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.909 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.909 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.910 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.910 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.911 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.911 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.912 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.912 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.913 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.913 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.913 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.914 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.914 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.915 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:41.915 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.282 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.282 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.320 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.321 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.321 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.356 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.357 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.357 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.392 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.392 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.393 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.428 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.428 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.429 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.463 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.465 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.465 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.501 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.502 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.502 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.536 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.537 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.537 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.573 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.574 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.574 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.609 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.609 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.610 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.645 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.647 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.648 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.684 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.685 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.685 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:42.721 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.245 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 8107
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.246 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.246 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.300 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.301 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.301 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.301 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.301 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.302 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.302 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.302 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.302 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.302 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.302 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.302 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.302 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.302 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.303 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.303 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.303 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.303 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.303 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.303 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.303 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.303 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.303 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.304 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.304 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.304 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.304 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.847 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.848 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.848 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.849 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.849 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.850 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.850 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.850 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.851 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.851 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.852 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.852 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.853 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.853 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.853 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.854 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.854 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.855 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.855 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:46.855 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.312 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.313 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.352 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.353 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.353 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.394 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.396 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.397 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.437 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.440 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.441 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.482 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.484 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.485 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.525 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.527 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.528 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.568 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.570 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.570 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.611 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.612 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.613 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:47.613 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.152 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.152 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.193 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.195 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.196 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.236 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.237 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.237 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.279 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.279 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.280 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.323 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.324 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.324 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.363 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.364 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.364 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.405 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.406 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.406 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.446 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.446 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.447 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.486 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.486 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.486 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.528 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.528 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.529 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.568 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.571 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.571 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.571 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.571 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.571 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.571 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.571 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.571 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.571 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.571 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.572 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.572 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.572 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.572 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.572 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.572 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.572 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.572 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.572 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.572 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.572 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.572 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.572 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.573 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.573 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:48.573 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.110 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.111 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.152 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.154 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.155 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.195 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.195 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.196 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.236 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.239 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.240 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.280 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.281 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.281 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.321 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.322 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.322 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.362 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.364 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.365 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.405 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.407 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.408 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.448 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.448 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.449 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.489 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.489 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.490 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.530 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.531 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.531 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.571 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.573 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.573 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.614 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.616 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.617 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.657 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.658 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.658 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.658 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.658 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.658 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.658 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.658 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.658 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.658 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.658 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.658 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.658 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.658 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.659 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.659 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.659 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.659 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.659 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.659 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:49.659 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.073 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.074 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.114 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.114 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.115 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.154 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.155 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.156 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.196 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.198 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.199 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.239 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.240 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.240 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.280 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.282 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.283 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.323 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.324 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.324 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.364 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.364 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.365 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.405 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.406 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.406 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.446 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.446 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.447 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.486 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.487 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.488 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.528 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.528 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.529 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:50.568 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.267 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 8107
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.267 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.267 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.318 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.320 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.321 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.322 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.322 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.322 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.323 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.323 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.324 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.324 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.324 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.325 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.325 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.326 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.326 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.327 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.327 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.328 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.328 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.328 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.329 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.329 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.330 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.330 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.330 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.331 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.331 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.803 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.804 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.804 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.804 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.804 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.804 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.805 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.805 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.805 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.805 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.806 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.806 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.806 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.806 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.806 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.807 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.807 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.807 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.807 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:52.807 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.171 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.172 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.207 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.207 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.207 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.245 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.246 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.246 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.274 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.274 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.274 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.316 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.316 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.317 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.351 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.351 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.352 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.386 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.387 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.387 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.408 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.423 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.423 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.423 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.423 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.423 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.423 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.424 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.424 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.424 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.424 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.424 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.425 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.425 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.425 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.425 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.425 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.425 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.425 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.426 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.426 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.426 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.426 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.426 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.426 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.426 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.427 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.898 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.898 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.925 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.925 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.925 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.971 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.971 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:53.971 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.007 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.008 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.008 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.043 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.044 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.044 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.078 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.080 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.081 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.116 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.116 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.117 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.151 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.152 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.152 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.188 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.188 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.189 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.223 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.223 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.223 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.258 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.261 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.262 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.262 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.263 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.263 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.264 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.264 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.264 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.265 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.265 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.266 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.266 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.266 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.267 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.267 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.268 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.268 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.268 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.269 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.269 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.270 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.270 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.271 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.271 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.271 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.272 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.740 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.741 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.777 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.779 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.780 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.815 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.815 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.816 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.850 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.851 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.851 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.886 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.886 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.887 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.921 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.922 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.922 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.956 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.957 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.957 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.992 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.993 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:54.994 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.026 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.026 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.026 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.064 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.064 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.065 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.099 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.101 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.102 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.126 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.126 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.126 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.174 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.176 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.176 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.210 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.211 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.211 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.211 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.211 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.211 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.211 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.211 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.211 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.211 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.212 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.212 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.212 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.212 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.212 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.212 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.212 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.212 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.212 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.212 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.212 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.559 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.559 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.592 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.592 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.592 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.642 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.642 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.643 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.677 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.677 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.677 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.712 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.713 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.713 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.748 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.748 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:55.749 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:56.000 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:56.000 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:56.000 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:56.035 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:56.036 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:56.036 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:56.070 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:56.071 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:56.071 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:56.106 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:56.107 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:56.107 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:56.141 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:56.143 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:56.144 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:56.179 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:56.181 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:56.182 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:45:56.216 DEBUG 948 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.739 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 8107
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.739 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.739 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.789 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.791 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.793 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.794 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.794 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.795 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.796 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.796 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.797 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.798 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.798 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.799 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.799 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.800 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.800 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.801 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.801 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.801 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.802 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.802 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.802 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.803 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.803 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.804 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.804 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.804 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:00.805 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.253 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.253 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.253 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.253 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.253 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.253 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.253 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.253 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.254 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.254 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.254 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.254 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.254 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.254 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.254 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.254 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.254 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.254 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.255 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.255 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.599 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.599 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.631 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.631 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.631 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.666 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.666 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.666 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.700 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.701 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.701 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.734 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.735 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.735 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.768 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.770 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.770 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.804 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.806 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.807 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.841 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.842 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.842 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.842 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.842 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.842 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.842 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.842 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.842 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.842 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.842 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.842 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.842 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.843 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.843 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.843 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.843 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.843 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.843 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.843 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.843 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.843 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.843 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.843 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.843 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.843 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:01.843 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.327 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.328 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.362 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.364 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.365 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.398 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.398 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.399 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.431 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.431 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.432 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.465 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.467 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.468 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.501 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.504 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.504 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.537 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.538 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.538 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.572 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.573 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.573 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.605 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.606 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.606 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.640 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.641 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.641 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.674 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.675 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.675 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.675 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.675 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.675 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.675 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.675 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.675 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.675 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.675 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.676 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.676 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.676 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.676 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.676 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.676 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.676 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.676 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.676 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.676 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.676 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.676 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.676 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.677 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.677 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:02.677 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.122 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.122 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.156 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.156 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.157 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.193 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.195 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.196 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.229 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.229 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.230 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.262 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.263 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.263 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.284 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.284 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.284 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.330 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.332 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.332 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.351 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.367 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.367 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.404 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.406 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.407 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.440 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.440 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.440 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.473 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.473 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.474 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.506 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.507 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.507 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.540 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.540 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.541 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.567 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.919 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.919 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.952 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.952 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.952 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.983 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.983 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:03.983 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.023 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.024 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.024 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.057 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.058 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.058 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.068 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 8107
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.068 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.068 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.092 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.092 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.093 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.124 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 35
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.125 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.125 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.125 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.125 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.125 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.126 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.126 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.126 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.126 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.126 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.126 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.126 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.126 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.126 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.126 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.127 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.127 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.127 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.127 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.127 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.127 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.127 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.127 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.127 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.127 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.127 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.127 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.127 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.128 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.167 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.169 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.170 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.211 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.211 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.212 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.251 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.253 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.254 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.295 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.297 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.298 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.339 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.339 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.340 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.380 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.576 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.576 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.576 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.576 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.576 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.576 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.576 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.576 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.576 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.576 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.576 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.576 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.577 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.577 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.577 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.577 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.577 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.577 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.577 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.577 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.919 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.919 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.952 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.952 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.953 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.985 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.987 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:04.987 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.020 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.021 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.021 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.055 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.056 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.056 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.086 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.086 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.086 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.122 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.122 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.123 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.156 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.157 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.157 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.157 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.157 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.157 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.157 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.158 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.158 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.158 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.158 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.158 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.158 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.158 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.158 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.158 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.159 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.159 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.159 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.159 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.159 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.159 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.159 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.159 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.159 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.160 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.160 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.602 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.602 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.642 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.642 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.642 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.676 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.677 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.677 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.710 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.711 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.711 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.744 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.746 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.747 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.780 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.783 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.783 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.807 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.807 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.807 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.853 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.856 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.856 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.887 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.887 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.887 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.923 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.924 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.924 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.958 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.959 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.959 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.959 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.959 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.959 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.959 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.959 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.959 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.959 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.959 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.959 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.959 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.960 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.960 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.960 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.960 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.960 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.960 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.960 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.960 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.960 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.960 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.960 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.960 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.960 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:05.960 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.406 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.406 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.439 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.440 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.440 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.474 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.476 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.477 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.510 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.510 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.511 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.544 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.545 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.545 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.577 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.578 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.578 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.611 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.612 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.612 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.646 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.646 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.647 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.680 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.682 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.683 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.716 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.718 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.719 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.752 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.752 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.753 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.786 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.787 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.787 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.820 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.822 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.822 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.855 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.856 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.856 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.856 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.856 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.856 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.856 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.856 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.856 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.856 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.856 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.857 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.857 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.857 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.857 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.857 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.857 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.857 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.857 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.857 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:06.857 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.230 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.230 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.264 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.265 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.265 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.297 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.298 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.298 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.332 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.332 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.333 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.366 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.367 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.367 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.400 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.400 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.401 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.433 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.434 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.434 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.467 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.468 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.468 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.501 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.501 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.502 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.535 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.535 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.536 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.569 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.570 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.570 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.603 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.603 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.603 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:07.637 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:53.362 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:53.362 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:53.378 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:53.379 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:53.379 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:53.395 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:53.799 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:53.799 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:56.554 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:56.554 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:56.584 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:56.585 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:56.586 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:56.606 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:58.058 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:46:58.058 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:00.794 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:00.794 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:00.811 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:00.812 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:00.812 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:01.568 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:02.335 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:02.335 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.699 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 8679
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.699 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.700 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.749 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 49
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.750 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.750 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.750 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.750 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.750 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.751 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.751 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.751 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.751 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.751 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.751 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.751 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.751 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.752 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.752 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.752 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.752 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.752 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.752 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.752 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.752 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.752 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.752 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.752 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.753 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:19.753 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.428 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.785 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.785 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.819 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.820 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.820 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.845 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.845 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.845 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.889 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.889 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.890 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.912 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.912 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.912 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.957 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.959 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.960 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.993 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.995 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:20.995 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.029 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.030 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.030 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.030 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.031 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.032 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.480 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.480 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.513 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.515 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.516 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.550 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.552 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.553 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.587 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.588 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.588 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.620 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.621 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.621 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.655 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.657 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.658 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.691 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.691 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.692 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.725 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.726 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.726 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.758 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.759 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.759 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.793 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.795 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.796 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.830 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.831 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.831 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.831 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.831 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.831 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.831 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.831 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.831 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.832 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.832 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.832 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.832 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.832 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.832 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.832 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.832 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.832 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.832 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.833 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.833 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.833 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.833 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.833 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.833 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.833 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:21.833 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.286 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.287 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.321 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.323 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.324 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.357 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.358 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.358 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.391 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.393 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.394 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.427 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.429 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.430 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.463 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.466 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.467 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.501 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.503 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.503 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.536 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.537 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.537 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.571 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.572 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.572 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.605 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.606 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.606 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.639 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.639 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.640 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.673 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.674 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.674 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.707 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.709 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.709 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.742 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.743 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.743 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.743 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.744 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.744 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.744 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.744 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.744 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.745 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.745 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.745 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.745 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.745 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.745 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.746 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.746 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.746 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.746 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.746 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:22.747 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.091 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.092 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.126 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.127 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.127 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.160 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.161 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.161 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.195 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.198 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.199 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.233 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.233 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.233 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.268 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.268 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.269 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.302 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.303 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.303 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.336 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.336 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.337 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.370 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.372 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.372 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.406 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.407 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.407 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.440 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.440 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.441 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.473 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.474 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.474 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:23.508 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.262 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 8679
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.263 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.263 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 42
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.311 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.871 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.872 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.872 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.872 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.872 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.872 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.872 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.872 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.872 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.872 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.872 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.872 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.872 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.873 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.873 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.873 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.873 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.873 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.873 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:37.873 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.293 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.293 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.335 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.335 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.336 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.376 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.377 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.377 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.419 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.419 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.419 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.460 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.462 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.463 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.504 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.504 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.505 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.545 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.546 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.546 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.586 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.587 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.587 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.587 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.587 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.587 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.587 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.587 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.587 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.587 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.587 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.587 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.587 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.588 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.588 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.588 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.588 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.588 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.588 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.588 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.588 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.588 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.588 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.588 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.588 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.588 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.589 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.648 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 8679
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.648 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.648 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.698 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.700 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.701 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 1.一种并联连接的谐振转换器电路(String), 1.一种并联连接的谐振转换器电路(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.702 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：多个谐振转换器(String), 包含：多个谐振转换器(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.702 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.703 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 直流电源(String), 直流电源(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.703 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具正端与负端(String), 具正端与负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.703 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 输出电容(String), 输出电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.704 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及多个输入电容(String), 以及多个输入电容(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.704 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.705 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.705 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.705 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.706 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.706 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.707 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.707 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.707 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.708 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.708 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.709 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.709 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.709 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.710 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.710 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.711 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:38.711 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739997(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要1(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.138 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.138 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.179 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.179 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.179 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.179 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.179 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.179 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.179 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.179 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 每一输入电容具第一端与第二端(String), 每一输入电容具第一端与第二端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.180 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.180 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.180 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.180 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.180 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.180 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.180 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.180 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.180 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.180 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.181 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.181 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.181 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.181 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.181 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 739998(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要2(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.222 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.222 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.223 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.263 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.264 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.264 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.304 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.304 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.305 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.345 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.346 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.346 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.387 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.387 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.388 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.428 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.430 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.431 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.471 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.471 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.472 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.512 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.513 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.513 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.541 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.542 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 739999(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.554 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.556 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.557 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.557 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.558 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.558 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.559 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.559 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.559 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.559 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.559 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.559 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.559 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.560 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.560 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.560 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.560 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.560 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.560 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.560 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.560 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.560 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.560 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.560 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.560 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.560 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.561 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.564 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.564 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.564 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 740000(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.612 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.613 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.613 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 740001(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.647 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.649 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.650 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 740002(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.681 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.681 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.681 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 740003(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.721 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.722 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.722 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 740004(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.748 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.748 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.748 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 740005(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.794 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.796 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.796 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 10.一种谐振转换器电路(String), 10.一种谐振转换器电路(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.796 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：至少第一与第二谐振转换器(String), 包含：至少第一与第二谐振转换器(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.796 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 各所述谐振转换器具两个输入端与两个输出端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.796 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.797 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第一谐振转换器的所述两个输入端(String), 连接于所述第一谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.797 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第一输入电压Vin1(String), 且提供第一输入电压Vin1(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.797 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.797 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 连接于所述第二谐振转换器的所述两个输入端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.797 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供第二输入电压Vin2(String), 且提供第二输入电压Vin2(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.797 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.797 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.797 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且提供输出电压Vo(String), 且提供输出电压Vo(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.797 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.797 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.797 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.797 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.798 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.798 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.798 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.798 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.798 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.798 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.798 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.798 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:39.798 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740006(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要10(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.108 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.108 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.149 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.151 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.151 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.192 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.192 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.192 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.233 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.234 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.234 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.264 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.265 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 740007(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要11(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.275 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.277 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.278 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.298 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.300 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.300 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 740008(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要12(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.318 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.319 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.319 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.334 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.335 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.336 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 740009(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要13(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.359 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.360 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.360 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.370 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.371 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.371 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 740010(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要14(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.401 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.402 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.402 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.406 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.407 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.407 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 740011(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要15(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.441 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.442 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.443 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.444 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 740012(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要16(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.444 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.445 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.480 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.481 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.481 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.484 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.484 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.485 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740013(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要17(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.515 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.516 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.517 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.528 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.529 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.529 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 740014(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要18(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.551 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.553 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.554 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.569 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.570 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.570 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 740015(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要19(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.588 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.590 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.590 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.611 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.612 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.612 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 740016(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要20(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.624 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.624 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.625 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.625 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.625 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.625 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.625 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.625 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.625 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.625 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.625 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.625 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.625 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.626 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.626 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.626 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.626 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.626 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.626 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.626 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.626 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.653 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.655 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.655 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 21.一种谐振转换器电路(String), 21.一种谐振转换器电路(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.655 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.655 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.655 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二谐振转换器(String), 第二谐振转换器(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.655 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.655 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.656 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.656 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.656 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.656 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第一输入电容(String), 第一输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.656 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.656 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 第二输入电容(String), 第二输入电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.656 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.656 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及输出电容(String), 以及输出电容(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.656 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.656 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.656 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.656 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.656 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.656 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 20(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.657 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 21(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.657 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 22(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.657 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 23(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.657 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 24(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.657 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740017(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要21(String), 1(Integer), 25(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.985 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:40.985 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.020 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.020 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.021 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.055 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.055 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.055 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.083 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.083 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.083 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.125 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.125 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.126 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.148 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.148 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.148 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.195 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.197 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.198 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.201 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.201 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 740018(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要22(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.233 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.233 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.234 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.242 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.242 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.243 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740019(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要23(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.268 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.268 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.268 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.283 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.283 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.284 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740020(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要24(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.302 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.302 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.303 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.324 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.325 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.325 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 740021(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要25(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.338 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.338 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.339 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.364 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.364 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.364 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 740022(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要26(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.364 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.364 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.364 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.398 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.398 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.398 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.398 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 740023(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要27(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.432 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.432 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.432 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740024(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要28(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.478 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.479 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.479 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740025(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要29(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.513 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.515 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.516 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740026(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要30(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.551 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.552 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.552 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740027(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要31(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.586 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.587 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.587 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740028(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要32(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.621 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.622 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.622 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740029(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要33(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.657 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.658 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.658 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740030(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要34(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 35.一种谐振转换器电路(String), 35.一种谐振转换器电路(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 包含：第一谐振转换器(String), 包含：第一谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及第二谐振转换器(String), 以及第二谐振转换器(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 6(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 7(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 8(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 9(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 10(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 11(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 12(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 13(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 14(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 15(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 16(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 17(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 18(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:41.682 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 则停止(String), 则停止(String), 740031(Integer), 154(Integer), 0(Integer), 163(Integer), 2(Integer), 权要35(String), 1(Integer), 19(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.052 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.052 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 740032(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要36(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.086 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.088 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.089 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 740033(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要37(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.125 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.125 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.126 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 740034(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要38(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.160 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.161 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.161 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 740035(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要39(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.196 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.197 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.197 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 740036(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要40(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.231 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.233 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.234 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 740037(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要41(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.267 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.268 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.268 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 740038(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要42(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.303 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.304 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.304 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 740039(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要43(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.338 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.339 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.339 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 740040(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要44(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.374 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.376 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.377 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 740041(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要45(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.411 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.412 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.412 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 740042(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要46(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.446 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.447 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.447 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN102522896B(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 740043(Integer), 154(Integer), 0(Integer), 163(Integer), -1(Integer), 权要47(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 12:47:42.481 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:02:21.802 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 13:02:21.803 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:02:21.821 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:02:21.826 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:02:21.826 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:02:21.845 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:02:21.845 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage ==>  Preparing: SELECT ID,CREATE_TIME,TASK_NAME,PROGRESS,TASK_STATUS,CREATE_ID,CREATE_NAME,BEGIN_TIME,FINISH_TIME,END_TIME,TYPE,REPORT_ID,HANDLE_PERSON_ID,HANDLE_PERSON_NAME,REMARK,RESULT,SIGN_PATENT_NO FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 13:02:21.845 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage ==> Parameters: 0(Integer), 154(Integer), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:02:21.862 DEBUG 948 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.812 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.812 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.828 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.828 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.830 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.845 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.845 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.845 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.853 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.853 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.862 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.862 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.862 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.870 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.870 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.870 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.888 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.889 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.889 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.907 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.909 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.910 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:02.927 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:03.149 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:03.859 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:03.859 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:03.878 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:05.967 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:05.968 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:05.985 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:05.985 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:05.985 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:06.002 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:06.003 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:06.003 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:06.019 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:06.020 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:06.020 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:05:06.037 DEBUG 948 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.760 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.761 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.777 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.777 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.777 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.795 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.795 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.795 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.812 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.812 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.813 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.826 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.827 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 163(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.830 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.830 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.830 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.847 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.890 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.890 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:03.907 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:16.955 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 8891
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:16.955 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:16.956 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:16.974 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:17.015 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? 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[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:17.046 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 1.一种并联连接的谐振转换器电路(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 包含：多个谐振转换器(String), 以及输出电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 直流电源(String), 且提供输出电压Vo(String), 具正端与负端(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 输出电容(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 以及多个输入电容(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 每一输入电容具第一端与第二端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 且在动态情况下能够自动达到平衡点(String), 则停止(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 21.一种谐振转换器电路(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 第二谐振转换器(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 具两个输入端与两个输出端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 第二输入电容(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 则停止(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 21.一种谐振转换器电路(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 包含：第一谐振转换器(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 具两个输入端与两个输出端(String), 则停止(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 1.一种并联连接的谐振转换器电路(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 包含：多个谐振转换器(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 直流电源(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 具正端与负端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 输出电容(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 以及多个输入电容(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一输入电容具第一端与第二端(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 则停止(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 1.一种并联连接的谐振转换器电路(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含：多个谐振转换器(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 具正端与负端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 输出电容(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 以及多个输入电容(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 每一输入电容具第一端与第二端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 则停止(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 10.一种谐振转换器电路(String), 每一输入电容具第一端与第二端(String), 包含：至少第一与第二谐振转换器(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 第一输入电容(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 连接于所述第一谐振转换器的所述两个输入端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 且提供第一输入电压Vin1(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 第二输入电容(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 连接于所述第二谐振转换器的所述两个输入端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 且提供第二输入电压Vin2(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 以及输出电容(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 且提供输出电压Vo(String), 则停止(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 21.一种谐振转换器电路(String), 则停止(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 21.一种谐振转换器电路(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 包含：第一谐振转换器(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 具两个输入端与两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 则停止(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 35.一种谐振转换器电路(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 包含：第一谐振转换器(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 具两个输入端与两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 则停止(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 35.一种谐振转换器电路(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 包含：第一谐振转换器(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 具两个输入端与两个输出端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 且在动态情况下能够自动达到平衡点(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 则停止(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 每一谐振转换器具两个输入端与两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 每一输入电容具第一端与第二端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 则停止(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 1.一种并联连接的谐振转换器电路(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 包含：多个谐振转换器(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 具正端与负端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 输出电容(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 以及多个输入电容(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 每一输入电容具第一端与第二端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 则停止(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 21.一种谐振转换器电路(String), 且在动态情况下能够自动达到平衡点(String), 包含：第一谐振转换器(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 具两个输入端与两个输出端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 第二谐振转换器(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 具两个输入端与两个输出端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 且在动态情况下能够自动达到平衡点(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 第一输入电容(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 则停止(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 每一谐振转换器具两个输入端与两个输出端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 每一输入电容具第一端与第二端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 则停止(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 35.一种谐振转换器电路(String), 连接于所述第一谐振转换器的所述两个输入端(String), 包含：第一谐振转换器(String), 且提供第一输入电压Vin1(String), 具两个输入端与两个输出端(String), 第二输入电容(String), 以及第二谐振转换器(String), 连接于所述第二谐振转换器的所述两个输入端(String), 具两个输入端与两个输出端(String), 且提供第二输入电压Vin2(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 以及输出电容(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且提供输出电压Vo(String), 且在动态情况下能够自动达到平衡点(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 且在动态情况下能够自动达到平衡点(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 则停止(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 1.一种并联连接的谐振转换器电路(String), 以及输出电容(String), 包含：多个谐振转换器(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 每一谐振转换器具两个输入端与两个输出端(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 直流电源(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 具正端与负端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 输出电容(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 以及多个输入电容(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 每一输入电容具第一端与第二端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 则停止(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 35.一种谐振转换器电路(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 包含：第一谐振转换器(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 具两个输入端与两个输出端(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 以及第二谐振转换器(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 具两个输入端与两个输出端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 则停止(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 35.一种谐振转换器电路(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 包含：第一谐振转换器(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 具两个输入端与两个输出端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 且在动态情况下能够自动达到平衡点(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 则停止(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 每一谐振转换器具两个输入端与两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 每一输入电容具第一端与第二端(String), 则停止(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 1.一种并联连接的谐振转换器电路(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 包含：多个谐振转换器(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一谐振转换器具两个输入端与两个输出端(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 直流电源(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 具正端与负端(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 输出电容(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及多个输入电容(String), 则停止(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 10.一种谐振转换器电路(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含：至少第一与第二谐振转换器(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 各所述谐振转换器具两个输入端与两个输出端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 第一输入电容(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 连接于所述第一谐振转换器的所述两个输入端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 且提供第一输入电压Vin1(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 第二输入电容(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 连接于所述第二谐振转换器的所述两个输入端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 且提供第二输入电压Vin2(String), 则停止(String), 以及输出电容(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 且提供输出电压Vo(String), 每一谐振转换器具两个输入端与两个输出端(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且在动态情况下能够自动达到平衡点(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 21.一种谐振转换器电路(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 包含：第一谐振转换器(String), 且提供输出电压Vo(String), 具两个输入端与两个输出端(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 第二谐振转换器(String), 且在动态情况下能够自动达到平衡点(String), 具两个输入端与两个输出端(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 且在动态情况下能够自动达到平衡点(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 第一输入电容(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 第二输入电容(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 则停止(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 21.一种谐振转换器电路(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 包含：第一谐振转换器(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 具两个输入端与两个输出端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 第二谐振转换器(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 具两个输入端与两个输出端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 且在动态情况下能够自动达到平衡点(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 第一输入电容(String), 则停止(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 以及输出电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 每一输入电容具第一端与第二端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 则停止(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 35.一种谐振转换器电路(String), 且提供第一输入电压Vin1(String), 包含：第一谐振转换器(String), 第二输入电容(String), 具两个输入端与两个输出端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及第二谐振转换器(String), 以及输出电容(String), 具两个输入端与两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 且提供输出电压Vo(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 35.一种谐振转换器电路(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 包含：第一谐振转换器(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 具两个输入端与两个输出端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及第二谐振转换器(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 具两个输入端与两个输出端(String), 则停止(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 每一谐振转换器具两个输入端与两个输出端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一输入电容具第一端与第二端(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 则停止(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 1.一种并联连接的谐振转换器电路(String), 以及输出电容(String), 包含：多个谐振转换器(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 且提供输出电压Vo(String), 直流电源(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 具正端与负端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 输出电容(String), 且在动态情况下能够自动达到平衡点(String), 以及多个输入电容(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 每一输入电容具第一端与第二端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 且在动态情况下能够自动达到平衡点(String), 则停止(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 21.一种谐振转换器电路(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 包含：第一谐振转换器(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 具两个输入端与两个输出端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 第二谐振转换器(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 具两个输入端与两个输出端(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 则停止(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 1.一种并联连接的谐振转换器电路(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 包含：多个谐振转换器(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 直流电源(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 具正端与负端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 输出电容(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 以及多个输入电容(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一输入电容具第一端与第二端(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 则停止(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 21.一种谐振转换器电路(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含：第一谐振转换器(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 具两个输入端与两个输出端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 且在动态情况下能够自动达到平衡点(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 第二输入电容(String), 则停止(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 每一谐振转换器具两个输入端与两个输出端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 每一输入电容具第一端与第二端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 则停止(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 35.一种谐振转换器电路(String), 第一输入电容(String), 包含：第一谐振转换器(String), 连接于所述第一谐振转换器的所述两个输入端(String), 具两个输入端与两个输出端(String), 且提供第一输入电压Vin1(String), 以及第二谐振转换器(String), 第二输入电容(String), 具两个输入端与两个输出端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且提供输出电压Vo(String), 且在动态情况下能够自动达到平衡点(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 且在动态情况下能够自动达到平衡点(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 1.一种并联连接的谐振转换器电路(String), 第二输入电容(String), 包含：多个谐振转换器(String), 连接于所述第二谐振转换器的所述两个输入端(String), 每一谐振转换器具两个输入端与两个输出端(String), 且提供第二输入电压Vin2(String), 直流电源(String), 以及输出电容(String), 具正端与负端(String), 输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 以及多个输入电容(String), 且提供输出电压Vo(String), 每一输入电容具第一端与第二端(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 且在动态情况下能够自动达到平衡点(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 且在动态情况下能够自动达到平衡点(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 则停止(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 21.一种谐振转换器电路(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 各所述谐振转换器具两个输入端与两个输出端(String), 以及输出电容(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 连接于所述第一谐振转换器的所述两个输入端(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 且提供第一输入电压Vin1(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 第二输入电容(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 以及输出电容(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 且提供输出电压Vo(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 则停止(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 21.一种谐振转换器电路(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 第二谐振转换器(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 具两个输入端与两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 且在动态情况下能够自动达到平衡点(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 且在动态情况下能够自动达到平衡点(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 第一输入电容(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 第二输入电容(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及输出电容(String), 则停止(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 则停止(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:17.313 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:19.176 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:19.176 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:19.194 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:19.194 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:19.194 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:19.212 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:19.212 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:19.212 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:19.230 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:19.278 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:19.278 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:06:19.296 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:02.415 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:02.415 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:02.435 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:02.435 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:02.436 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:02.456 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:02.456 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:02.456 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 166(Integer), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:02.475 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:02.496 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:02.496 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:02.516 DEBUG 948 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.273 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.273 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.274 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.274 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.291 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.291 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.292 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.293 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.294 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.294 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.309 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.309 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.309 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.313 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.313 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.313 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.326 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.326 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.326 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.332 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.332 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.332 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.344 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.353 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.353 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.353 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.359 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.359 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.372 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.376 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.377 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.377 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.395 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.414 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.415 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.432 DEBUG 948 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.520 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.520 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 163(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.611 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:06.611 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:30.272 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 8891
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:30.273 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:30.273 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:30.291 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:30.332 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? 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[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:30.363 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 1.一种并联连接的谐振转换器电路(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 包含：多个谐振转换器(String), 以及输出电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 直流电源(String), 且提供输出电压Vo(String), 具正端与负端(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 输出电容(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 以及多个输入电容(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 每一输入电容具第一端与第二端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 且在动态情况下能够自动达到平衡点(String), 则停止(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 21.一种谐振转换器电路(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 第二谐振转换器(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 具两个输入端与两个输出端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 第二输入电容(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 则停止(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 21.一种谐振转换器电路(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 包含：第一谐振转换器(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 具两个输入端与两个输出端(String), 则停止(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 1.一种并联连接的谐振转换器电路(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 包含：多个谐振转换器(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 直流电源(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 具正端与负端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 输出电容(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 以及多个输入电容(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一输入电容具第一端与第二端(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 则停止(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 1.一种并联连接的谐振转换器电路(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含：多个谐振转换器(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 具正端与负端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 输出电容(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 以及多个输入电容(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 每一输入电容具第一端与第二端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 则停止(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 10.一种谐振转换器电路(String), 每一输入电容具第一端与第二端(String), 包含：至少第一与第二谐振转换器(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 各所述谐振转换器具两个输入端与两个输出端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 第一输入电容(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 连接于所述第一谐振转换器的所述两个输入端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 且提供第一输入电压Vin1(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 第二输入电容(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 连接于所述第二谐振转换器的所述两个输入端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 且提供第二输入电压Vin2(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 以及输出电容(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 且提供输出电压Vo(String), 则停止(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 21.一种谐振转换器电路(String), 则停止(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 21.一种谐振转换器电路(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 包含：第一谐振转换器(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 具两个输入端与两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 则停止(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 35.一种谐振转换器电路(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 包含：第一谐振转换器(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 具两个输入端与两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 则停止(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 35.一种谐振转换器电路(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 包含：第一谐振转换器(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 具两个输入端与两个输出端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 且在动态情况下能够自动达到平衡点(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 则停止(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 每一谐振转换器具两个输入端与两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 每一输入电容具第一端与第二端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 则停止(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 1.一种并联连接的谐振转换器电路(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 包含：多个谐振转换器(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 具正端与负端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 输出电容(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 以及多个输入电容(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 每一输入电容具第一端与第二端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 则停止(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 21.一种谐振转换器电路(String), 且在动态情况下能够自动达到平衡点(String), 包含：第一谐振转换器(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 具两个输入端与两个输出端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 第二谐振转换器(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 具两个输入端与两个输出端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 且在动态情况下能够自动达到平衡点(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 第一输入电容(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 则停止(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 每一谐振转换器具两个输入端与两个输出端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 每一输入电容具第一端与第二端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 则停止(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 35.一种谐振转换器电路(String), 连接于所述第一谐振转换器的所述两个输入端(String), 包含：第一谐振转换器(String), 且提供第一输入电压Vin1(String), 具两个输入端与两个输出端(String), 第二输入电容(String), 以及第二谐振转换器(String), 连接于所述第二谐振转换器的所述两个输入端(String), 具两个输入端与两个输出端(String), 且提供第二输入电压Vin2(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 以及输出电容(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且提供输出电压Vo(String), 且在动态情况下能够自动达到平衡点(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 且在动态情况下能够自动达到平衡点(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 则停止(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 1.一种并联连接的谐振转换器电路(String), 以及输出电容(String), 包含：多个谐振转换器(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 每一谐振转换器具两个输入端与两个输出端(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 直流电源(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 具正端与负端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 输出电容(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 以及多个输入电容(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 每一输入电容具第一端与第二端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 则停止(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 35.一种谐振转换器电路(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 包含：第一谐振转换器(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 具两个输入端与两个输出端(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 以及第二谐振转换器(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 具两个输入端与两个输出端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 则停止(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 35.一种谐振转换器电路(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 包含：第一谐振转换器(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 具两个输入端与两个输出端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 且在动态情况下能够自动达到平衡点(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 则停止(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 每一谐振转换器具两个输入端与两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 每一输入电容具第一端与第二端(String), 则停止(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 1.一种并联连接的谐振转换器电路(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 包含：多个谐振转换器(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一谐振转换器具两个输入端与两个输出端(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 直流电源(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 具正端与负端(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 输出电容(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及多个输入电容(String), 则停止(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 10.一种谐振转换器电路(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含：至少第一与第二谐振转换器(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 各所述谐振转换器具两个输入端与两个输出端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 第一输入电容(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 连接于所述第一谐振转换器的所述两个输入端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 且提供第一输入电压Vin1(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 第二输入电容(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 连接于所述第二谐振转换器的所述两个输入端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 且提供第二输入电压Vin2(String), 则停止(String), 以及输出电容(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 且提供输出电压Vo(String), 每一谐振转换器具两个输入端与两个输出端(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且在动态情况下能够自动达到平衡点(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 21.一种谐振转换器电路(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 包含：第一谐振转换器(String), 且提供输出电压Vo(String), 具两个输入端与两个输出端(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 第二谐振转换器(String), 且在动态情况下能够自动达到平衡点(String), 具两个输入端与两个输出端(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 且在动态情况下能够自动达到平衡点(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 第一输入电容(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 第二输入电容(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 则停止(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 21.一种谐振转换器电路(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 包含：第一谐振转换器(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 具两个输入端与两个输出端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 第二谐振转换器(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 具两个输入端与两个输出端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 且在动态情况下能够自动达到平衡点(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 第一输入电容(String), 则停止(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 以及输出电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 每一输入电容具第一端与第二端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 则停止(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 35.一种谐振转换器电路(String), 且提供第一输入电压Vin1(String), 包含：第一谐振转换器(String), 第二输入电容(String), 具两个输入端与两个输出端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及第二谐振转换器(String), 以及输出电容(String), 具两个输入端与两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 且提供输出电压Vo(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 35.一种谐振转换器电路(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 包含：第一谐振转换器(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 具两个输入端与两个输出端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及第二谐振转换器(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 具两个输入端与两个输出端(String), 则停止(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 每一谐振转换器具两个输入端与两个输出端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一输入电容具第一端与第二端(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 则停止(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 1.一种并联连接的谐振转换器电路(String), 以及输出电容(String), 包含：多个谐振转换器(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 且提供输出电压Vo(String), 直流电源(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 具正端与负端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 输出电容(String), 且在动态情况下能够自动达到平衡点(String), 以及多个输入电容(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 每一输入电容具第一端与第二端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 且在动态情况下能够自动达到平衡点(String), 则停止(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 21.一种谐振转换器电路(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 包含：第一谐振转换器(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 具两个输入端与两个输出端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 第二谐振转换器(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 具两个输入端与两个输出端(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 则停止(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 1.一种并联连接的谐振转换器电路(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 包含：多个谐振转换器(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 每一谐振转换器具两个输入端与两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 直流电源(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 具正端与负端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 输出电容(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 以及多个输入电容(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 每一输入电容具第一端与第二端(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 则停止(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 21.一种谐振转换器电路(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 包含：第一谐振转换器(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 具两个输入端与两个输出端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 且在动态情况下能够自动达到平衡点(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 第二输入电容(String), 则停止(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 每一谐振转换器具两个输入端与两个输出端(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 每一输入电容具第一端与第二端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 则停止(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 35.一种谐振转换器电路(String), 第一输入电容(String), 包含：第一谐振转换器(String), 连接于所述第一谐振转换器的所述两个输入端(String), 具两个输入端与两个输出端(String), 且提供第一输入电压Vin1(String), 以及第二谐振转换器(String), 第二输入电容(String), 具两个输入端与两个输出端(String), 连接于所述第二谐振转换器的所述两个输入端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且提供输出电压Vo(String), 且在动态情况下能够自动达到平衡点(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 且在动态情况下能够自动达到平衡点(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 第二输入电容(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 以及输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 且提供输出电压Vo(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 21.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 以及输出电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 1.一种并联连接的谐振转换器电路(String), 包含：多个谐振转换器(String), 每一谐振转换器具两个输入端与两个输出端(String), 直流电源(String), 具正端与负端(String), 输出电容(String), 以及多个输入电容(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 各所述谐振转换器具两个输入端与两个输出端(String), 第一输入电容(String), 连接于所述第一谐振转换器的所述两个输入端(String), 且提供第一输入电压Vin1(String), 1.一种并联连接的谐振转换器电路(String), 第二输入电容(String), 包含：多个谐振转换器(String), 连接于所述第二谐振转换器的所述两个输入端(String), 每一谐振转换器具两个输入端与两个输出端(String), 且提供第二输入电压Vin2(String), 直流电源(String), 以及输出电容(String), 具正端与负端(String), 输出电容(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 以及多个输入电容(String), 且提供输出电压Vo(String), 每一输入电容具第一端与第二端(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 且并联电连接于所述多个谐振转换器中特定转换器的所述两个输入端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 其中所述输出电容并联电连接于每一谐振转换器的所述两个输出端(String), 且在动态情况下能够自动达到平衡点(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 各所述谐振转换器之间的输出电流的差别仅决定于各所述谐振转换器直流电压增益的差别(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 且在动态情况下能够自动达到平衡点(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 其中当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 则停止(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 则停止(String), 2.一种并联连接的谐振转换器电路的控制方法(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 其中所述电路包括多个谐振转换器、具有正端与负端的直流电源、输出电容以及多个输入电容(String), 每一谐振转换器具两个输入端与两个输出端(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 每一谐振转换器的所述两个输入端串联电连接于其余的所述多个谐振转换器的各所述两个输入端(String), 且每一谐振转换器的所述两个输出端并联电连接于其余的所述多个谐振转换器的各所述两个输出端(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 每一输入电容具第一端与第二端(String), 且并联电连接于所述多个谐振转换器中对应转换器的所述两个输入端(String), 其中所述输出电容并联电连接于所述多个谐振转换器中所述对应转换器的所述两个输出端(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 且各所述串联电连接的谐振转换器并联电连接于所述直流电源的所述正端与所述负端(String), 包含下列的步骤：当流经所述多个谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 当所述多个谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 3.如权利要求2所述的方法，其中所述则停止步骤更包括：当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述多个谐振转换器中另一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述特定谐振转换器的直流电压增益的倒数与所述另一谐振转换器的直流电压增益的倒数两者间的比值时，则所述特定谐振转换器与所述另一谐振转换器两者间重新达到平衡(String), 21.一种谐振转换器电路(String), 4.如权利要求2所述的方法，其中所述多个谐振转换器包括第一与第二谐振转换器，所述特定谐振转换器为所述第二谐振转换器，所述则停止步骤更包括：当流经所述第二谐振转换器的所述两个输出端的所述输出电流与所述第一谐振转换器的所述两个输出端的所述输出电流间的比值等于所述第二谐振转换器的直流电压增益的倒数与所述第一谐振转换器的直流电压增益的倒数两者间的比值时，则所述第一与所述第二谐振转换器两者间重新达到平衡(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 5.如权利要求2所述的方法，其中所述多个谐振转换器工作于交错的工作模式(String), 第二谐振转换器(String), 具两个输入端与两个输出端(String), 6.如权利要求2所述的方法，其中所述多个谐振转换器工作于相同的频率(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 7.如权利要求2所述的方法，其中所述多个谐振转换器包括串联谐振直流/直流转换器与并联谐振直流/直流转换器(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 8.如权利要求7所述的方法，其中所述串联谐振直流/直流转换器是LLC串联谐振直流/直流转换器(String), 且在动态情况下能够自动达到平衡点(String), 第一输入电容(String), 9.如权利要求7所述的方法，其中所述并联谐振直流/直流转换器是LLC并联谐振直流/直流转换器(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 第二输入电容(String), 10.一种谐振转换器电路(String), 包含：至少第一与第二谐振转换器(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 各所述谐振转换器具两个输入端与两个输出端(String), 以及输出电容(String), 第一输入电容(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 连接于所述第一谐振转换器的所述两个输入端(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 且提供第一输入电压Vin1(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 第二输入电容(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 连接于所述第二谐振转换器的所述两个输入端(String), 且提供第二输入电压Vin2(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 以及输出电容(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 并联电连接所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 且提供输出电压Vo(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 其中产生第一输出电流Io1的所述第一谐振转换器的所述两个输出端的其中之一是连接于另一产生第二输出电流Io2的所述第二谐振转换器的所述两个输出端的其中之一(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 其中当流经所述至少第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 则停止(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高(String), 当所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述至少第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 11.如权利要求10所述的电路，其中各所述输入电压Vin1与Vin2各自与所述第一谐振转换器与所述第二谐振转换器的第一增益M1与第二增益M2成比例(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 12.如权利要求10所述的电路，其中所述至少第一与第二谐振转换器工作于交错的工作模式(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 13.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器工作于相同的频率(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 14.如权利要求10所述的电路，其中各所述至少第一与第二谐振转换器是LLC串联谐振直流/直流转换器(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 15.如权利要求10所述的电路，其中各所述两个输入端是串联电连接，且各所述两个输出端是并联电连接(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 16.如权利要求10所述的电路，其中所述第二谐振转换器的所述两个输入端是串联电连接于所述第一谐振转换器的所述两个输入端，且所述第二谐振转换器的所述两个输出端是并联电连接于所述第一谐振转换器的所述两个输出端(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 17.如权利要求10所述的电路，其中所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 18.如权利要求17所述的电路，其中所述第一谐振转换器的所述第一增益M1是所述输出电压Vo除以所述第一输入电压Vin1，且所述第二谐振转换器的所述第二增益M2是所述输出电压Vo除以所述第二输入电压Vin2(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 19.如权利要求17所述的电路，其中所述第一输出电流Io1是来自所述第一谐振转换器的所述两个输入端的其中之一的第一输入电流Iin1除以所述第一谐振转换器的所述第一增益M1，且所述第二输出电流Io2是来自所述第二谐振转换器的所述两个输入端的其中之一的第二输入电流Iin2除以所述第二谐振转换器的所述第二增益M2(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 20.如权利要求19所述的电路，其中在稳定条件下，所述第一输入电流Iin1与所述第二输入电流Iin2相同，且所述第一输出电流Io1除以所述第二输出电流Io2与所述第二谐振转换器的所述第二增益M2除以所述第一谐振转换器的所述第一增益M1是相同的(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 21.一种谐振转换器电路(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 第二谐振转换器(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 具两个输入端与两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 且在动态情况下能够自动达到平衡点(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 且在动态情况下能够自动达到平衡点(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 第一输入电容(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 耦接于所述第一谐振转换器的所述两个输入端之间(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 第二输入电容(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 耦接于所述第二谐振转换器的所述两个输入端之间(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 以及输出电容(String), 则停止(String), 耦接于所述第一谐振转换器的所述两个输出端与所述第二谐振转换器的所述两个输出端之间(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 当所述特定谐振转换器的所述两个输入端的所述输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 当所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的输出电流升高(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的所述两个输出端的所述输出电流重新达到平衡时(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 则停止(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 22.如权利要求21所述的电路，更包括：第三谐振转换器，具两个输入端与两个输出端，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端；以及第三输入电容，耦接于所述第三谐振转换器的所述两个输入端之间，其中所述输出电容耦接于所述第三谐振转换器的所述两个输出端之间(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 23.如权利要求22所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 24.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 25.如权利要求22所述的电路，其中所述第一与所述第二谐振转换器的直流增益不同(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 26.如权利要求22所述的电路，其中所述第一谐振转换器具有第一输出电流Io1，且所述第二谐振转换器具有第二输出电流Io2(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 27.如权利要求26所述的电路，其中当Io1≠Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2间的差别所决定(String), 28.如权利要求27所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 29.如权利要求27所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 30.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 31.如权利要求22所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 32.如权利要求22所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String), 33.如权利要求22所述的电路，其中所述第一输入电容与所述第二输入电容所分别提供的输入电压Vin1与Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 34.如权利要求33所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 35.一种谐振转换器电路(String), 包含：第一谐振转换器(String), 具两个输入端与两个输出端(String), 以及第二谐振转换器(String), 具两个输入端与两个输出端(String), 其中所述第一谐振转换器的所述两个输入端串联电连接于所述第二谐振转换器的所述两个输入端(String), 所述第一谐振转换器的所述两个输出端并联电连接于所述第二谐振转换器的所述两个输出端(String), 所述第一与所述第二谐振转换器之间的输出电流的差别仅决定于所述第一与所述第二谐振转换器直流电压增益的差别(String), 且在动态情况下能够自动达到平衡点(String), 其中当流经所述第一与第二谐振转换器中特定谐振转换器的所述两个输出端的输出电流升高时(String), 使得流经所述特定谐振转换器的所述两个输入端的输入电流亦升高(String), 当流经所述特定谐振转换器的所述两个输入端的输入电流升高时(String), 使得所述特定谐振转换器的所述两个输入端的输入电压降低(String), 当特定谐振转换器的所述两个输入端的输入电压降低时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的所述两个输入端的输入电压升高(String), 当所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输入端的输入电压升高时(String), 使得所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的输出电流升高(String), 以及当流经所述特定谐振转换器的所述两个输出端的所述输出电流与所述第一与第二谐振转换器中其余的谐振转换器的各所述两个输出端的所述输出电流重新达到平衡时(String), 则停止(String), 36.如权利要求35所述的电路，更包括具两个输入端与两个输出端的第三谐振转换器，其中所述第三谐振转换器的所述两个输入端串联电连接于所述第一与所述第二谐振转换器的各所述两个输入端，且所述第三谐振转换器的所述两个输出端并联电连接于所述第一与所述第二谐振转换器的各所述两个输出端(String), 37.如权利要求36所述的电路，其中所述第一、所述第二与所述第三谐振转换器的频率相同(String), 38.如权利要求35所述的电路，其中所述第一与所述第二谐振转换器的频率相同(String), 39.如权利要求35所述的电路，其中所述第一谐振转换器的第一增益M1与所述第二谐振转换器的第二增益M2不同(String), 40.如权利要求35所述的电路，更包括第一输入电容与第二输入电容，其中所述第一输入电容与所述第二输入电容所分别提供的第一输入电压Vin1与第二输入电压Vin2各自与所述第一谐振转换器的第一增益M1和所述第二谐振转换器的第二增益M2成比例(String), 41.如权利要求40所述的电路，其中在所述谐振转换器电路的稳定条件下，M2/M1＝Vin1/Vin2(String), 42.如权利要求35所述的电路，其中当所述第一谐振转换器的第一输出电流Io1≠所述第二谐振转换器的第二输出电流Io2时，所述第一输出电流Io1与所述第二输出电流Io2的差别是由所述第一谐振转换器的第一直流增益M1与所述第二谐振转换器的第二直流增益M2间的差别所决定(String), 43.如权利要求42所述的电路，其中在所述谐振转换器电路的稳定条件下，Io1/Io2＝M2/M1(String), 44.如权利要求42所述的电路，其中当Io1/Io2≠M2/M1时，一个自动电流平衡过程被执行(String), 45.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器工作于交错的工作模式(String), 46.如权利要求35所述的电路，其中所述第一谐振转换器与所述第二谐振转换器是同一类型(String), 47.如权利要求35所述的电路，其中各所述谐振转换器是LLC串联谐振直流/直流转换器(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:30.634 DEBUG 948 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:31.280 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:31.281 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:31.299 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:31.299 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:31.299 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:31.316 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:35.227 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:35.227 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:36.001 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 8959
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:36.001 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:36.001 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:36.058 DEBUG 948 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 77
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:53.787 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:53.787 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:53.808 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:53.808 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:53.808 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:53.827 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:53.827 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:53.827 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:53.847 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:53.847 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:53.847 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:53.867 DEBUG 948 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:53.872 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:53.872 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:54.202 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:54.202 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:54.202 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:54.222 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:55.892 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 8959
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:55.893 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:55.893 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:55.941 DEBUG 948 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:56.284 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:16:56.284 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:17:10.847 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 8882
[rms:0.0.0.0:8885] [,] 2022-12-12 13:17:10.847 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:17:10.847 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 163(Integer), CN102522896B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 13:17:10.883 DEBUG 948 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.342 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.362 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.398 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.402 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.404 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.424 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 3
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.434 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.435 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 167(Integer), 166(Integer), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.452 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.482 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.482 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.500 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.502 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.502 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.524 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.527 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.527 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.548 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.549 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.549 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.568 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.570 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.570 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:20.590 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:21.104 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:21.105 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:21.125 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:21.131 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:21.131 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:21.151 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:21.151 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage ==>  Preparing: SELECT ID,CREATE_TIME,TASK_NAME,PROGRESS,TASK_STATUS,CREATE_ID,CREATE_NAME,BEGIN_TIME,FINISH_TIME,END_TIME,TYPE,REPORT_ID,HANDLE_PERSON_ID,HANDLE_PERSON_NAME,REMARK,RESULT,SIGN_PATENT_NO FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:21.152 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage ==> Parameters: 0(Integer), 154(Integer), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:21.172 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.544 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.545 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.563 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.564 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.564 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.584 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.590 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.591 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.596 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.596 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.610 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.611 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.612 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.614 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.615 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.615 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.633 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.633 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.635 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.635 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.653 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.654 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.655 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.672 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.673 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.674 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:23.691 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:24.230 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:24.230 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:24.250 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:24.269 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:24.270 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:24.289 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:24.291 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:24.291 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:24.311 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:24.312 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:24.312 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:24.333 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.215 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.215 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.430 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.430 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.451 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.454 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.454 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.493 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.494 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.494 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.496 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.496 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.516 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.517 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.518 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.519 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.537 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.540 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.540 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.561 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.564 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.565 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:29.583 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:30.143 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:30.144 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:30.164 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:30.166 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:30.167 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:30.186 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:30.188 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:30.189 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:30.210 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:30.212 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:30.212 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:26:30.232 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:36.005 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:36.006 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:36.023 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:36.025 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:36.025 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:36.042 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:36.043 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:36.043 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:36.060 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:36.061 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:36.061 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:36.078 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:37.001 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:37.002 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:37.019 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:37.020 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:37.020 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:37.038 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:38.027 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:38.027 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:38.045 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:38.051 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:38.051 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:38.068 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:38.075 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:38.075 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:38.094 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:38.101 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:38.101 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:38.117 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:41.391 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:41.391 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:41.392 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:41.392 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:41.408 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:41.409 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:41.411 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:41.411 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:41.428 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:41.637 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:41.637 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:41.654 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:42.757 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:42.758 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:42.789 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:42.814 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:42.814 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2896(Integer), 4780(Integer), 5(Integer), JP2003093227A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:51.855 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:51.856 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:51.873 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:51.893 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:51.894 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:51.912 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:51.913 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:51.913 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:51.929 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:51.930 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:51.930 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:51.930 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:51.930 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:51.946 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:51.948 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:51.949 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:51.950 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:51.966 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:52.471 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:52.471 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:52.489 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:52.493 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:52.493 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:52.509 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:52.510 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:52.510 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:52.527 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:52.528 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:52.529 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:52.546 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:53.408 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:53.408 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:53.431 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:53.707 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:53.707 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:53.739 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:53.740 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:53.741 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:53.742 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:53.742 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:53.757 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:53.759 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:53.759 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2896(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:53.770 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 14:34:53.777 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.106 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.106 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.108 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.108 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.124 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.125 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.125 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.126 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.143 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.144 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.144 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.151 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.151 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.160 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.161 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.161 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.167 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.178 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.688 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.688 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.705 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.706 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.706 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.722 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.723 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.723 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.739 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.740 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.740 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:45.757 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:46.665 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:46.666 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:46.683 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:46.965 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:46.965 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:46.981 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:46.982 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:46.983 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:46.999 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:46.999 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:47.000 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:47.001 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:47.001 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2896(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:47.016 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:47.017 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:49.588 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:49.588 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:49.620 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:49.656 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:49.656 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2896(Integer), 4780(Integer), 5(Integer), JP2003093227A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:49.657 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2897(Integer), 4780(Integer), 5(Integer), JP2003093227A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:52.281 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:52.281 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:52.302 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:53.470 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:53.470 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:53.488 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:53.492 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:53.493 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:53.493 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:53.494 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:53.509 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:53.509 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:53.510 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:53.510 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:53.516 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:53.516 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:53.516 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:53.545 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:54.813 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:54.814 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:54.831 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.015 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.015 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.032 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.033 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.033 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.034 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.034 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.051 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.051 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.055 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.055 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.073 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.074 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.074 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.091 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.489 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.490 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.523 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.540 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:56.540 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2896(Integer), 4780(Integer), 5(Integer), JP2003093227A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:58.585 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:58.585 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:35:58.617 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:00.273 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:00.274 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:00.307 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:00.323 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:00.323 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2896(Integer), 4780(Integer), 5(Integer), JP2003093227A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:08.315 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:08.315 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:08.315 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:08.315 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:08.343 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:08.344 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:08.344 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:08.344 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:08.361 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:08.362 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:08.362 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2896(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:08.378 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:08.385 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:08.385 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:36:08.402 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:09.742 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:09.742 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:09.759 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:10.338 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:10.338 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:10.355 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:10.356 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:10.356 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:10.372 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:10.373 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:10.374 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:10.390 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:10.391 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:10.391 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:10.407 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:10.678 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:10.679 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:10.696 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:18.362 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:18.362 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:18.379 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:18.932 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:18.933 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:18.950 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:18.951 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:18.951 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:18.967 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:18.970 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:18.971 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:18.987 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:18.988 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:18.988 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:19.005 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:19.267 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:19.268 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:37:19.284 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:08.590 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:08.590 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:08.607 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:11.950 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:11.951 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:11.968 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:15.974 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:15.974 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:15.990 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:15.996 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:15.996 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.015 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.016 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.016 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.019 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.019 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.029 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.029 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.029 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.029 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.044 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.044 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.044 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.069 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.555 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.555 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.563 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.563 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.563 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.591 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.593 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.594 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.611 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.612 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.612 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:16.629 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:18.935 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:18.936 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:18.953 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:19.513 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:19.513 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), KR1020160016352A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:19.530 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:19.833 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:19.833 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:19.863 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:29.375 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:29.375 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:29.392 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:29.976 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:29.976 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), US20110256287A1(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:29.993 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:30.314 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:30.315 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:30.331 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:42.382 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:42.383 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:40:42.399 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:32.403 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:32.404 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:32.405 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:32.405 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:32.421 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:32.422 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:32.422 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:32.422 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:32.438 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:32.647 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:32.647 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:32.664 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:33.851 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:33.852 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: US20110256287A1(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:33.884 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:33.905 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:33.905 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2896(Integer), 4780(Integer), 5(Integer), US20110256287A1(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:36.659 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:36.660 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:36.677 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:37.269 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:37.269 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), KR1020160016352A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:37.286 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:37.603 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:37.603 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:37.620 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:38.385 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:38.385 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: KR1020160016352A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:38.419 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:38.454 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:38.455 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2896(Integer), 4780(Integer), 5(Integer), KR1020160016352A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:38.455 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2897(Integer), 4780(Integer), 5(Integer), KR1020160016352A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:38.836 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:38.837 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: KR1020160016352A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:38.869 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:38.887 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:38.887 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2897(Integer), 4780(Integer), 5(Integer), KR1020160016352A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:40.354 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:40.355 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:40.372 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:40.968 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:40.968 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), US20110256287A1(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:40.986 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:41.305 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:41.305 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:41.323 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:42.546 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:42.548 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:42.564 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:43.127 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:43.128 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), KR1020160016352A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:43.145 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:43.458 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:43.459 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:43.476 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:44.830 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:44.831 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:44.847 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:45.433 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:45.433 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:45.448 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:45.448 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:45.448 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:45.468 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:45.469 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:45.469 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:45.486 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:45.487 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:45.487 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:45.503 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:45.771 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:45.772 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:45.790 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:49.606 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:49.606 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:49.623 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:50.170 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:50.171 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), KR1020160016352A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:50.188 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:50.487 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:50.487 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:50.514 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:51.912 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:51.912 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:51.929 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:52.520 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:52.520 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:52.537 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:52.539 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:52.539 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:52.555 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:52.556 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:52.556 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:52.573 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:52.574 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:52.574 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:52.588 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:52.861 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:52.861 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:44:52.878 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:10.533 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:10.534 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:10.567 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:12.227 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:12.228 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:12.260 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:12.279 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:12.280 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2897(Integer), 4780(Integer), 5(Integer), CN102727071A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.076 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.076 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.093 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.096 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.096 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.113 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.113 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.114 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.114 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.114 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.130 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.131 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.131 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.131 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.148 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.149 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.149 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.167 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.696 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.697 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.714 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.717 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.717 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.734 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.735 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.735 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.751 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.752 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.752 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:49:44.769 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:12.646 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:12.646 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:12.647 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:12.647 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:12.663 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:12.664 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:12.664 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:12.664 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:12.680 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:12.681 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:12.681 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:12.697 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:12.976 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:12.976 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:12.994 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:25.386 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:25.386 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:25.418 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:25.867 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:25.868 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:25.900 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:25.918 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 14:51:25.918 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2897(Integer), 4780(Integer), 5(Integer), CN102727071A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.085 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.086 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.087 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.087 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.102 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.106 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.107 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.107 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.125 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.127 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.128 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.134 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.134 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.148 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.149 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.150 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.151 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.175 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.716 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.716 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.732 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.733 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.733 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.750 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.751 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.751 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.769 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.772 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.772 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:00.792 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:06.272 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:06.272 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:06.273 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:06.273 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:06.289 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:06.289 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:06.291 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:06.291 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:06.308 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:06.309 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:06.310 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:06.326 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:06.534 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:06.534 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:06.551 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:09.337 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:09.337 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:09.370 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:10.116 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:10.116 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:10.148 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:10.166 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 14:52:10.166 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2897(Integer), 4780(Integer), 5(Integer), CN102727071A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:13.277 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:13.277 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:13.294 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:13.294 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:13.294 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:13.315 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 3
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:13.316 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:13.316 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 167(Integer), 166(Integer), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:13.332 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:13.355 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:13.355 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:13.379 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:16.675 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:16.675 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==> Parameters: 167(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:16.692 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:16.692 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:16.693 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==> Parameters: 167(Integer), %%(String), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:16.711 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:16.712 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:16.712 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==> Parameters: 167(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:16.725 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:45.810 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:45.810 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:45.826 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.119 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.119 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.136 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.137 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.137 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.153 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.153 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.154 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.154 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.154 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.171 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.171 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.172 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.172 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.189 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.459 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.459 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.475 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.476 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.476 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.492 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.493 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.493 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.509 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.510 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.510 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:46.526 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:57.654 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:57.654 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:57.654 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:57.654 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:57.670 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:57.670 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:57.671 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:57.671 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:57.684 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:57.684 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:57.684 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:57.706 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:57.915 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:57.915 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:53:57.931 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:00.075 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:00.075 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:00.109 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:00.994 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:00.995 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:01.028 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:01.049 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:01.050 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2897(Integer), 4780(Integer), 5(Integer), CN102727071A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:36.165 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:36.166 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:36.182 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:41.363 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:41.364 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:41.382 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:41.384 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:41.385 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:41.402 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:41.403 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:41.403 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:41.419 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:41.420 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:41.420 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:41.437 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:57.808 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:57.824 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:54:57.858 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:00.539 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:00.539 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:00.572 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:00.592 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:00.592 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2897(Integer), 4780(Integer), 5(Integer), CN102727071A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:22.210 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:22.211 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:22.227 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:23.474 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:23.475 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:23.492 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:23.495 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:23.495 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:23.510 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:23.511 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:23.512 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:23.512 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:23.512 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:23.527 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:23.530 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:23.531 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:23.531 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:23.547 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:26.287 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:26.288 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:26.307 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:27.625 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:27.626 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:27.642 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:27.642 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:27.643 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:27.644 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:27.644 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:27.659 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:27.661 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:27.662 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:27.662 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:27.687 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:27.688 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:27.688 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:27.706 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:29.169 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:29.170 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:29.186 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:30.382 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:30.382 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:30.399 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:30.400 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:30.400 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:30.415 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:30.415 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:30.416 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:30.416 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:30.416 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:30.432 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:30.433 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:30.435 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:30.435 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:30.452 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:33.067 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:33.067 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:33.100 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:34.406 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:34.406 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:34.439 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:34.457 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 14:55:34.457 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2897(Integer), 4780(Integer), 5(Integer), JP2003093227A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.743 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.744 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.762 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.763 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.763 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.781 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.782 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.782 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.800 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.800 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.800 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.818 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.819 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.819 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.837 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.837 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.837 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.843 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.843 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.843 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.881 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.885 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.885 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:11.903 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:12.160 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:12.161 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:12.179 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:12.188 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:12.188 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:12.207 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:15.258 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:15.258 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:15.275 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:18.349 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:18.366 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:18.384 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:18.387 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:18.387 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:18.408 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:18.409 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:18.409 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:18.427 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:18.428 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:18.429 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:18.447 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:18.718 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:18.720 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:18.737 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:20.743 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:20.743 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:20.745 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:20.746 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:20.760 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:20.765 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:20.766 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:20.766 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:20.785 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:20.787 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:20.787 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:20.805 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:20.997 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:20.997 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:21.016 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:22.189 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:22.190 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:22.226 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:22.263 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:22.263 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2897(Integer), 4780(Integer), 5(Integer), CN102727071A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:22.264 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2896(Integer), 4780(Integer), 5(Integer), CN102727071A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:25.337 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:25.337 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:25.356 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:25.932 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:25.932 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:25.952 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:25.955 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:25.955 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:25.973 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:25.974 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:25.974 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:25.993 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:25.994 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:25.994 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:26.012 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:26.258 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:26.259 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:26.279 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:27.066 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:27.066 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:27.066 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:27.066 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:27.082 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:27.084 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:27.085 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:27.085 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:27.103 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:27.104 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:27.104 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:27.122 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:27.325 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:27.325 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:27.353 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:33.938 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:33.938 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:33.957 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:35.149 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:35.149 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:35.165 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:35.165 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:35.165 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:35.165 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:35.165 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:35.183 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:35.183 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:35.183 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:35.183 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:35.215 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:35.219 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:35.219 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:35.232 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:35.907 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:35.907 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:35.926 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:36.219 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:36.219 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:36.237 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:36.237 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:36.237 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:36.249 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:36.250 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:36.256 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:36.257 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:36.257 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2897(Integer), 2896(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:36.266 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:36.275 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:40.278 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:40.278 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:40.314 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:40.332 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:40.332 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2897(Integer), 4780(Integer), 5(Integer), CN102727071A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:41.741 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:41.741 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:41.759 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:42.932 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:42.932 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), KR1020160016352A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:42.951 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:42.962 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:42.962 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:42.981 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:43.669 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:43.669 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:43.688 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:43.978 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:43.978 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:43.997 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:43.998 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:43.998 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:44.011 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:44.011 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:44.016 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:44.016 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:44.016 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:44.027 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:44.035 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:45.229 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:45.229 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: KR1020160016352A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:45.265 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:45.301 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:45.302 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2897(Integer), 4780(Integer), 5(Integer), KR1020160016352A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:45.302 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2896(Integer), 4780(Integer), 5(Integer), KR1020160016352A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:46.183 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:46.183 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: KR1020160016352A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:46.219 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:46.236 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:46.237 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2896(Integer), 4780(Integer), 5(Integer), KR1020160016352A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:48.586 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:48.586 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:48.605 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:49.152 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:49.152 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:49.171 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:49.171 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:49.171 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:49.189 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:49.189 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:49.189 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:49.209 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:49.211 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:49.212 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:49.230 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:49.490 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:49.491 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:49.509 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:50.217 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:50.217 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:50.217 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:50.217 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:50.234 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:50.236 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:50.239 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:50.239 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:50.258 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:50.261 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:50.262 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:50.280 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:50.484 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:50.484 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:50.503 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:52.703 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:52.704 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:52.722 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:53.886 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:53.887 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:53.904 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:53.904 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:53.905 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:53.906 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:53.906 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:53.921 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:53.924 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:53.925 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:53.925 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:53.943 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:53.944 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:53.944 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:53.962 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:54.402 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:54.402 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:54.431 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:54.721 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:54.721 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:54.739 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:54.740 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:54.740 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:54.748 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:54.748 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:54.758 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:54.758 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:54.758 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:54.764 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:54.776 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:59.767 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:59.767 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:59.771 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:59.772 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:59.786 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:59.788 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:59.789 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:59.790 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:59.822 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:59.823 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:59.823 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:07:59.840 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:00.043 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:00.076 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:00.093 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:01.146 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:01.147 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:01.179 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:01.215 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:01.215 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2897(Integer), 4780(Integer), 5(Integer), JP2003093227A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:01.215 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2896(Integer), 4780(Integer), 5(Integer), JP2003093227A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:02.749 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:02.749 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:02.781 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:02.800 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:02.800 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2896(Integer), 4780(Integer), 5(Integer), JP2003093227A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:04.282 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:04.283 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:04.299 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:05.482 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:05.483 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:05.501 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:05.502 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:05.502 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:05.519 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:05.520 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:05.520 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:05.537 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:05.538 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:05.538 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:05.554 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:05.556 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:05.557 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:05.575 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:05.801 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:05.801 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:05.819 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:06.114 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:06.115 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:06.137 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:06.138 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:06.139 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:06.144 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:06.145 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:06.157 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:06.158 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:06.158 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:06.161 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:06.176 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:10.015 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:10.015 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:10.034 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:10.602 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:10.603 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:10.622 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:10.622 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:10.622 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:10.640 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:10.640 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:10.640 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:10.659 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:10.659 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:10.660 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:10.669 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:10.934 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:10.935 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:10.953 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:14.506 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:14.506 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:14.506 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:14.506 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:14.522 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:14.524 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:14.524 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:14.524 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:14.542 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:14.543 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:14.543 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2896(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:14.562 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:14.774 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:14.774 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:08:14.793 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:43.539 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:43.539 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:43.557 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:43.558 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:43.558 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:43.576 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:43.576 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:43.577 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:43.595 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:43.595 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:43.596 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:43.614 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:43.614 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:43.614 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2896(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:43.632 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:49.664 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:49.664 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:49.685 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:49.685 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:49.703 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:49.704 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:49.705 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:49.726 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:49.728 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:49.729 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:49.747 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:49.748 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:49.749 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:49.767 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:49.771 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:49.775 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:49.794 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:52.566 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:52.566 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:52.583 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:52.583 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:52.584 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:52.601 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:52.601 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:52.601 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:52.619 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:52.619 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:52.620 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:52.637 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:56.544 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:56.545 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:56.548 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:56.548 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:56.562 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:56.566 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:56.566 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:56.566 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:56.584 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:56.584 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:56.585 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2896(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:56.603 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:56.881 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:56.881 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:56.900 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:59.353 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:59.353 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:18:59.371 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:19:00.234 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:19:00.234 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), KR1020160016352A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:19:00.252 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:19:00.267 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:19:00.267 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:19:00.286 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:21:07.532 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:21:07.533 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:21:07.550 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:21:08.098 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:21:08.098 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), US20110256287A1(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:21:08.115 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:21:08.432 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:21:08.432 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:21:08.450 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:22:51.765 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:22:51.765 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:22:51.765 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:22:51.765 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:22:51.786 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:22:51.786 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:22:51.786 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:22:51.789 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:22:51.803 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:22:51.806 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:22:51.806 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2896(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:22:51.814 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:22:51.815 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:22:51.824 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:22:51.834 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:43.377 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:43.377 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:43.396 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:43.639 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:43.639 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:43.657 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:43.657 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:43.657 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:43.676 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:43.677 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:43.678 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:43.678 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:43.678 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:43.696 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:43.698 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:43.698 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:43.699 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:43.715 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:44.123 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:44.123 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), US20110256287A1(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:24:44.127 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:39.814 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:39.814 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:39.815 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:39.815 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:39.832 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:39.834 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:39.834 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:39.834 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:39.848 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:39.848 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:39.852 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:39.853 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:39.853 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:39.866 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:39.870 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:39.871 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:39.871 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:39.888 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:40.430 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:40.430 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), US20110256287A1(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:40.443 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:49.607 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:49.607 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:49.625 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:49.913 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:49.913 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:49.931 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:49.932 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:49.932 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:49.943 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:49.943 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:49.950 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:49.950 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:49.950 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2896(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:49.961 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:26:49.968 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:27:22.787 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:27:22.787 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:27:22.805 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:27:23.377 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:27:23.377 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), KR1020160016352A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:27:23.396 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:27:23.706 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:27:23.706 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:27:23.724 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:51.411 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:51.411 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:51.429 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:51.691 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:51.692 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:51.710 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:51.711 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:51.711 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:51.729 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:51.730 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:51.731 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:51.748 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:51.749 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:51.749 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:51.766 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:51.775 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:51.775 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:51.792 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:52.631 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:52.632 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:52.649 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:52.649 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:52.650 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:52.667 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:52.667 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:52.668 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:52.685 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:52.685 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:52.686 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:52.703 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:58.827 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:58.827 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:58.828 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:58.828 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:58.845 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:58.845 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:58.845 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:58.845 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:58.864 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:58.866 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:58.867 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2896(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:58.884 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:59.092 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:59.092 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:29:59.110 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:10.859 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:10.860 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:10.878 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:12.066 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:12.066 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:12.084 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:12.084 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:12.084 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:12.085 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:12.085 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:12.101 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:12.103 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:12.103 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:12.104 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:12.121 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:12.122 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:12.122 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:12.140 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:35.819 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:35.820 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:35.838 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:36.092 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:36.092 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:36.092 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:36.092 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:36.109 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:36.110 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:36.110 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:36.110 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:36.127 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:36.128 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:36.128 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:30:36.146 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:06.786 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:06.786 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:06.808 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.085 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.086 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.103 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.103 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.103 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.103 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.103 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.120 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.121 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.121 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.121 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.140 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.140 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.141 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.158 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.721 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.721 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.738 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.739 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.739 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.757 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.758 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.758 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.776 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.777 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.777 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:07.795 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.065 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.065 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.065 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.065 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.083 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.085 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.085 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.086 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.103 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.106 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.106 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.107 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.107 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.123 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.124 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.124 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.126 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.141 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.664 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.665 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.682 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.683 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.683 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.700 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.700 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.700 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.717 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.718 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.718 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:31:28.735 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:01.638 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:01.638 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:01.638 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:01.638 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:01.655 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:01.655 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:01.655 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:01.656 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:01.673 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:01.675 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:01.676 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:01.693 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:01.885 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:01.885 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:01.903 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:06.796 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:06.796 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:06.814 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:07.988 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:07.988 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:07.989 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:07.989 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), KR1020160016352A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:08.006 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:08.007 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:08.022 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:08.022 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:08.040 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:08.254 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:08.254 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:32:08.273 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:36:58.247 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:36:58.247 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:36:58.248 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:36:58.248 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:36:58.266 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:36:58.266 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:36:58.267 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:36:58.267 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:36:58.277 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:36:58.278 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:36:58.284 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:36:58.284 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:36:58.284 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2896(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:36:58.296 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:36:58.300 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:04.887 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:04.887 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:04.890 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:04.890 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:04.906 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:04.908 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:04.909 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:04.909 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:04.927 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:04.927 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:04.927 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:04.935 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:04.935 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:04.945 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:04.946 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:04.946 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:04.952 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:04.964 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:05.499 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:05.500 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), KR1020160016352A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:05.518 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:08.230 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:08.230 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:08.230 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:08.230 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:08.248 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:08.248 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:08.249 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:08.249 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:08.267 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:08.267 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:08.268 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2896(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:08.285 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:08.489 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:08.489 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:08.508 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:10.152 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:10.152 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: KR1020160016352A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:10.189 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:11.860 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:11.860 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:11.878 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:12.443 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:12.443 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), US20110256287A1(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:12.466 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:12.758 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:12.758 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:12.775 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:12.775 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:12.778 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:12.779 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:12.779 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:12.792 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:12.792 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:12.792 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:12.792 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2896(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:12.807 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:15.067 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:15.067 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:15.085 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:15.654 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:15.654 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), KR1020160016352A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:15.672 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:15.957 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:15.957 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:15.975 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:15.975 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:15.976 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:15.976 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:15.976 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:15.992 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:15.994 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:19.111 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:19.111 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:19.130 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:19.691 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:19.691 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:19.709 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:19.709 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:19.709 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:19.728 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:19.728 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:19.728 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:19.747 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:19.747 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:19.747 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:19.765 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:20.000 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:20.000 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:20.019 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:20.019 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:20.019 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:20.034 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:20.034 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:20.036 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:20.037 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:20.037 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:20.051 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:20.055 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:22.483 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:22.484 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:22.502 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.001 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.001 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.019 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.020 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.020 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.038 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.038 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.038 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.056 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.056 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.057 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.075 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.306 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.307 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.324 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.325 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.325 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.340 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.340 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.343 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.343 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.344 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2896(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.357 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:23.362 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:50.867 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM OS_PATENT_FIELD WHERE (NAME LIKE ? AND REPORT_TYPE LIKE ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:50.867 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==> Parameters: %%(String), %0%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:50.885 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:50.885 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (NAME LIKE ? AND REPORT_TYPE LIKE ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:50.886 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==> Parameters: %%(String), %0%(String), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:50.904 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectPage <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:50.904 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM OS_PATENT_FIELD WHERE (NAME LIKE ? AND REPORT_TYPE LIKE ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:50.904 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==> Parameters: %%(String), %0%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:37:50.913 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:03.568 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:03.568 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:03.586 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:03.586 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:03.586 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:03.606 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:03.606 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.TaskMapper.selectPage ==>  Preparing: SELECT ID,CREATE_TIME,TASK_NAME,PROGRESS,TASK_STATUS,CREATE_ID,CREATE_NAME,BEGIN_TIME,FINISH_TIME,END_TIME,TYPE,REPORT_ID,HANDLE_PERSON_ID,HANDLE_PERSON_NAME,REMARK,RESULT,SIGN_PATENT_NO FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:03.607 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.TaskMapper.selectPage ==> Parameters: 0(Integer), 154(Integer), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:03.625 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.TaskMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:06.443 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:06.443 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:06.461 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:06.462 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:06.462 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:06.479 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 3
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:06.480 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:06.480 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 167(Integer), 166(Integer), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:06.498 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:06.521 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:06.521 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:06.539 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.012 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.013 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.031 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.031 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.031 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.049 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 3
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.050 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.050 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 167(Integer), 166(Integer), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.068 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.089 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.089 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.090 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.091 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.106 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.107 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.107 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.109 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.124 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.124 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.125 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.141 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.142 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.142 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:10.159 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:18.703 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:18.703 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==> Parameters: 166(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:18.720 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:18.721 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:18.721 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==> Parameters: 166(Integer), %%(String), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:18.738 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:18.739 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:18.739 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==> Parameters: 166(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:18.756 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:41.587 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (NAME = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:41.587 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 初筛理由(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:41.604 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:41.629 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD ( NAME, PTYPE, TYPE, STATUS, REMARK, CID, REPORT_ID ) VALUES ( ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:41.630 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.insert ==> Parameters: 初筛理由(String), 1(Integer), 2(Integer), 1(Integer), (String), 154(Integer), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:41.666 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:41.992 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:41.992 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==> Parameters: 166(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:42.009 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:42.009 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:42.009 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==> Parameters: 166(Integer), %%(String), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:42.027 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectPage <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:42.027 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:42.027 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==> Parameters: 166(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:42.045 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:49.276 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.updateReportId ==>  Preparing: update OS_PATENT_FIELD set`NAME`=?,PTYPE=?,`TYPE`=?,STATUS=?,REMARK=?, CID=?,CREATE_TIME=?,REPORT_TYPE=? where REPORT_ID=? and ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:49.279 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.updateReportId ==> Parameters: 相关性(String), 1(Integer), 4(Integer), 1(Integer), (String), 114(Integer), 2022-12-12 10:19:53.0(Timestamp), 0(Integer), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:49.314 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.updateReportId <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:49.641 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:49.641 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==> Parameters: 166(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:49.658 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:49.658 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:49.658 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==> Parameters: 166(Integer), %%(String), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:49.675 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectPage <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:49.675 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:49.675 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==> Parameters: 166(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:49.693 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:56.965 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:56.965 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:56.966 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:56.966 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:56.982 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:56.982 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:56.982 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:56.985 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.000 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.000 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.000 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.002 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.002 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.017 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.017 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.017 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.020 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.035 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.540 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.541 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.558 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.558 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.558 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.574 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.574 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.575 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.589 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.589 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.589 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:57.607 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.003 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.003 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.004 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.004 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.021 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.022 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.022 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.022 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.039 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.039 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.039 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2896(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.057 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.058 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.058 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.075 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.268 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.268 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.286 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.347 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.347 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:39:59.364 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:02.103 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:02.103 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:02.138 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:02.157 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:02.158 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2897(Integer), 4780(Integer), 4(Integer), JP2003093227A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:16.165 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:16.165 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: JP2003093227A(String), 166(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:16.199 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:16.203 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:16.203 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:16.221 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:16.277 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:16.277 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:16.295 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:16.855 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:16.855 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), KR1020160016352A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:16.872 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:17.168 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:17.168 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:17.185 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:17.185 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:17.185 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:17.185 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:17.185 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:17.203 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:17.203 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:17.204 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:17.204 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:17.220 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:25.479 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:25.479 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: KR1020160016352A(String), 166(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:25.513 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:25.513 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:25.513 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:25.530 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:25.530 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldTextMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_TEXT ( NAME, CID ) VALUES ( ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:25.531 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldTextMapper.insert ==> Parameters: 相关性(String), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:25.565 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldTextMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:25.583 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:25.584 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 38326(Integer), 4784(Integer), 2(Integer), KR1020160016352A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:25.599 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:25.600 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: KR1020160016352A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:25.637 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:25.656 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:25.657 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2896(Integer), 4780(Integer), 4(Integer), KR1020160016352A(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:27.755 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:27.756 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:27.775 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:28.957 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:28.957 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:28.957 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), US20110256287A1(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:28.957 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:28.975 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:28.976 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:28.976 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:28.977 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:28.995 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:28.995 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:28.995 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2896(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:29.004 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:29.004 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:29.004 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:29.031 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:29.976 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:29.976 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:29.990 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:30.753 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:30.754 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: US20110256287A1(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:30.789 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:30.807 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:30.807 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 2897(Integer), 4780(Integer), 4(Integer), US20110256287A1(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:35.298 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:35.298 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: US20110256287A1(String), 166(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:35.333 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:35.333 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:35.333 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:35.351 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:35.351 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldTextMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_TEXT ( NAME, CID ) VALUES ( ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:35.351 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldTextMapper.insert ==> Parameters: 不相关(String), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:35.385 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldTextMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:35.403 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD_PATENT_LINK ( FID, CID, TYPE, PATENT_NO, REPORT_ID, USER_ID ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:35.403 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.insert ==> Parameters: 38327(Integer), 4784(Integer), 2(Integer), US20110256287A1(String), 166(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:36.562 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:36.577 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:36.594 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.781 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.781 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.781 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.781 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), KR1020160016352A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.797 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.797 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.799 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.799 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.799 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.800 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.815 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.817 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.818 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.818 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2896(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.836 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.838 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.838 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.857 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.860 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.861 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 38326(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:37.879 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:38.780 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:38.781 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:38.799 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:39.980 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:39.981 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:39.981 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:39.981 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:39.999 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:39.999 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:39.999 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.000 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.001 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.002 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.002 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.002 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.018 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.020 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.020 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.020 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.020 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.021 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.021 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.037 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.037 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.037 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.037 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.037 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.037 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.055 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:40.055 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:44.565 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:44.565 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: CN102727071A(String), 166(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:44.587 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:44.587 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:44.587 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:44.618 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:57.357 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM OS_PATENT_FIELD WHERE (NAME LIKE ? AND REPORT_TYPE LIKE ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:57.358 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==> Parameters: %%(String), %0%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:57.376 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:57.376 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (NAME LIKE ? AND REPORT_TYPE LIKE ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:57.376 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==> Parameters: %%(String), %0%(String), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:57.395 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectPage <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:57.395 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM OS_PATENT_FIELD WHERE (NAME LIKE ? AND REPORT_TYPE LIKE ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:57.395 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==> Parameters: %%(String), %0%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:40:57.413 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:00.672 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:00.673 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:00.691 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:00.696 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:00.696 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:00.714 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:00.714 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectPage ==>  Preparing: SELECT ID,CREATE_TIME,TASK_NAME,PROGRESS,TASK_STATUS,CREATE_ID,CREATE_NAME,BEGIN_TIME,FINISH_TIME,END_TIME,TYPE,REPORT_ID,HANDLE_PERSON_ID,HANDLE_PERSON_NAME,REMARK,RESULT,SIGN_PATENT_NO FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:00.714 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectPage ==> Parameters: 0(Integer), 154(Integer), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:00.733 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.779 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.779 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.796 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.796 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.796 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.815 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.815 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.815 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.834 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.834 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.835 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.839 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.839 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.839 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.839 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.839 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.856 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.858 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.858 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.858 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.875 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.876 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.876 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.893 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.893 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.893 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:03.911 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.428 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.429 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.448 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.448 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.448 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.466 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.466 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.467 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.484 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.485 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.485 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.503 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.504 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.504 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.523 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.524 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.524 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.542 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.544 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.544 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.561 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.561 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.561 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.579 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.579 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.580 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.598 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.599 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.599 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.616 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.616 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.616 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.635 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.636 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.636 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.653 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.653 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.653 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.672 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.675 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.675 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.692 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.693 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.693 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.712 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.712 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.712 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:04.730 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:05.584 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:05.584 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:05.591 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:05.591 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:05.591 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:05.606 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:05.622 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:05.622 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:05.640 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:05.641 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (CID = ? AND FID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:05.641 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: 4784(Integer), 38326(Integer), 38327(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:05.659 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:05.661 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:05.661 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:05.678 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:05.679 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:05.679 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:05.698 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:13.869 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:13.870 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:13.888 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:13.890 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:13.890 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:13.908 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:13.912 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:13.912 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:13.931 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:13.932 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (CID = ? AND FID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:13.932 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: 4780(Integer), 2896(Integer), 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:13.949 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:13.949 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:13.949 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:13.968 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:13.968 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:13.968 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:41:13.986 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:18.991 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:18.991 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.018 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.018 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.018 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.036 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.037 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.037 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.055 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.056 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.056 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.074 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.086 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.086 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.104 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.105 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.105 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.122 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.122 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage ==>  Preparing: SELECT ID,CREATE_TIME,TASK_NAME,PROGRESS,TASK_STATUS,CREATE_ID,CREATE_NAME,BEGIN_TIME,FINISH_TIME,END_TIME,TYPE,REPORT_ID,HANDLE_PERSON_ID,HANDLE_PERSON_NAME,REMARK,RESULT,SIGN_PATENT_NO FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.122 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage ==> Parameters: 0(Integer), 154(Integer), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.139 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.392 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.393 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.410 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.410 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.412 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.427 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.427 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.427 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.444 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.445 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.445 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.457 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.458 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.468 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.476 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.478 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.478 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.496 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.497 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.497 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.497 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.497 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.516 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.516 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.516 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.516 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.534 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.723 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.723 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.741 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.742 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.742 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.759 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.759 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.759 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.777 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.786 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.787 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.803 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.850 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.850 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.868 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.868 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.868 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.886 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.886 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.886 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.904 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.905 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.905 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:19.923 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.047 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.047 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.064 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.064 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.064 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.081 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.081 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.081 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.098 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.098 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.098 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.113 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.113 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.116 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.118 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.118 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.130 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.134 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.135 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.136 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.154 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.157 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.157 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.173 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.173 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.173 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.191 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.191 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.191 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.208 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.208 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.209 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.226 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.226 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.226 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.243 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.243 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.243 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.261 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.261 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.261 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.278 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.278 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.278 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.296 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.296 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.296 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.313 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.313 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.313 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.330 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.364 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.364 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.382 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.382 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.382 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.399 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.399 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.399 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.417 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.417 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.417 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.434 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.435 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.435 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.453 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.453 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.453 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.471 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.472 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.472 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.489 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.489 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.489 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.507 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.508 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.508 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.525 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.526 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.526 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.543 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.544 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.544 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.561 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.561 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.561 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.579 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.580 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.580 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.597 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.597 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.597 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.614 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.614 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.614 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.632 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.633 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.633 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:20.650 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:34.919 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:34.919 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:34.936 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.037 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.037 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.054 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.055 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.056 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.073 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.073 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.073 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.082 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.082 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.091 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.098 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.099 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.099 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.116 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.116 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.116 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.133 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.134 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.134 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.151 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.324 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.324 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.337 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.337 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.342 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.355 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.356 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.356 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.374 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.374 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.TaskMapper.selectPage ==>  Preparing: SELECT ID,CREATE_TIME,TASK_NAME,PROGRESS,TASK_STATUS,CREATE_ID,CREATE_NAME,BEGIN_TIME,FINISH_TIME,END_TIME,TYPE,REPORT_ID,HANDLE_PERSON_ID,HANDLE_PERSON_NAME,REMARK,RESULT,SIGN_PATENT_NO FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.374 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.TaskMapper.selectPage ==> Parameters: 0(Integer), 154(Integer), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.393 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.TaskMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.407 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.407 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.424 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.424 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.425 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.442 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.442 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.442 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.459 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.469 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.469 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.488 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.660 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.660 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.665 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.665 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.678 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.680 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.681 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.682 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.685 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.685 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.699 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.699 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.699 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.703 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.703 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.703 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.717 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.717 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.718 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.720 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.720 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.720 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.735 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.737 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.738 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.738 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.755 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.755 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.755 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.773 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.779 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.779 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.796 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.797 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.797 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.801 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.801 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.814 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.814 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.814 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.823 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.832 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.832 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.832 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.850 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.850 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.851 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.868 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.868 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.868 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.885 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.885 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.885 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.903 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.903 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.903 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.921 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.922 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.922 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.940 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.941 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.941 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:35.958 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.005 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.005 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.022 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.023 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.023 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.040 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.040 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.040 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.041 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.041 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.057 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.058 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.058 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.058 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.059 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.059 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.075 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.075 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.075 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.076 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.076 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.077 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.092 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.092 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.092 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.093 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.094 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.094 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.110 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.111 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.112 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.112 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.128 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.129 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.129 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.146 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.146 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.146 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.164 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.166 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.166 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.184 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.186 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.186 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.203 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.203 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.203 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.220 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.220 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.220 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.238 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.240 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.240 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.257 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.258 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.258 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.275 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.275 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.276 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:36.293 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:43.828 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM OS_PATENT_FIELD WHERE (NAME LIKE ? AND REPORT_TYPE LIKE ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:43.829 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==> Parameters: %%(String), %0%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:43.845 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:43.845 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (NAME LIKE ? AND REPORT_TYPE LIKE ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:43.845 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==> Parameters: %%(String), %0%(String), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:43.863 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectPage <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:43.863 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM OS_PATENT_FIELD WHERE (NAME LIKE ? AND REPORT_TYPE LIKE ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:43.863 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==> Parameters: %%(String), %0%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:43.880 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.023 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.023 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.040 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.042 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.042 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.060 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.062 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.062 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.079 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.079 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.080 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.097 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.113 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.113 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.130 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.131 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.131 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.148 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.148 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectPage ==>  Preparing: SELECT ID,CREATE_TIME,TASK_NAME,PROGRESS,TASK_STATUS,CREATE_ID,CREATE_NAME,BEGIN_TIME,FINISH_TIME,END_TIME,TYPE,REPORT_ID,HANDLE_PERSON_ID,HANDLE_PERSON_NAME,REMARK,RESULT,SIGN_PATENT_NO FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.148 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectPage ==> Parameters: 0(Integer), 154(Integer), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:54.167 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:55.930 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:55.930 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:55.948 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.125 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.125 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.126 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.126 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.143 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.143 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.143 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.144 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.144 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.144 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.161 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.161 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.161 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.161 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.162 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.162 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.178 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.178 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.178 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.178 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.178 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.178 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.196 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.196 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.248 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.248 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.265 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.266 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.266 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.283 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.283 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.283 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.300 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.310 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.310 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.328 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.508 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.508 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.526 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.526 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.527 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.545 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.547 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.548 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.566 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.566 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.566 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.583 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.640 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.641 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.659 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.763 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.764 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.782 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.782 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.782 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.800 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.800 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.801 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.818 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.818 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.818 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.836 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.836 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.836 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.853 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.853 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.853 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.870 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.870 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.870 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.872 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.872 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.887 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.888 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.888 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.890 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.890 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.890 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.905 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.906 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.906 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.907 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.907 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.907 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.922 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.923 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.923 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.925 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.925 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.925 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.940 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.942 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.942 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.942 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.944 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.945 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.959 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.961 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.962 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.962 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.964 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.964 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.979 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.982 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.984 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.984 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.988 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:56.988 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.000 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.000 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.000 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.000 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.000 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.000 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.020 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.021 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.021 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.023 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.023 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.023 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.039 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.039 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.039 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.041 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.041 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.041 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.046 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.046 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.046 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.046 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.075 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.075 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.075 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.092 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.092 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.092 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.110 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.110 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.110 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.127 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.128 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.128 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.144 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.145 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.145 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:57.162 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:58.861 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:58.861 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:58.877 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:58.877 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:58.879 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:58.895 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:58.897 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:58.898 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:58.915 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:58.915 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:58.915 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:58.932 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.151 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.151 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.151 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.151 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.169 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.169 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.169 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.169 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.187 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.187 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.187 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.205 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.206 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.206 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.224 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.495 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.495 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.512 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.512 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.512 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.529 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.529 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.529 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.546 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.547 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.548 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.564 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.564 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.564 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.581 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.582 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.582 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.600 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.607 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.608 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.625 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.625 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.625 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.642 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.642 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.642 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.659 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.660 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.660 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.677 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.677 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.677 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.694 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.695 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.695 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.710 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.711 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.711 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.729 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.729 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.729 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.746 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.746 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.746 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.763 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.763 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.763 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:43:59.781 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.292 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.292 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.308 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.309 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.311 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.326 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.326 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.326 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.344 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.344 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.344 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.352 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.353 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.354 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.354 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.361 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.370 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.371 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.371 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.371 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.388 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.388 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.389 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.407 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.407 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.407 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.425 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.955 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.955 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.972 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.974 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.974 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.992 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.992 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:02.992 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.009 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.009 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.009 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.027 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.027 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.027 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.044 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.044 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.044 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.061 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.063 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.063 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.068 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.068 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.068 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.100 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.102 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.102 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.120 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.120 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.120 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.136 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.137 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.137 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.154 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.154 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.154 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.172 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.172 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.172 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.189 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.189 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.189 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.207 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.208 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.208 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.224 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.225 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.225 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:03.242 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:32.407 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:32.408 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:32.408 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:32.408 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:32.425 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:32.425 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:32.425 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:32.426 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:32.427 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:32.427 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:32.431 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:32.431 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:32.431 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:32.431 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:32.446 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:32.446 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:32.446 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:32.477 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:33.300 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:33.301 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:33.318 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:33.318 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:33.318 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:33.336 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:33.336 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:33.336 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:33.353 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:33.353 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:33.353 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:33.371 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:46.552 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:46.552 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:46.569 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:46.569 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:46.570 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:46.587 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:46.782 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:46.782 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:44:46.809 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:16.230 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:16.231 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:16.247 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:16.247 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:16.248 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:16.266 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:16.453 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:16.453 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:16.481 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:29.222 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.LitigationHistoryMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM LITIGATION_HISTORY WHERE (PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:29.222 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.LitigationHistoryMapper.selectPage_mpCount ==> Parameters: CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:29.240 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.LitigationHistoryMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:29.723 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReferencesMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM PATENT_REFERENCES WHERE (PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:29.723 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReferencesMapper.selectPage_mpCount ==> Parameters: CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:29.740 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReferencesMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:31.071 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReviewHistoryMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REVIEW_HISTORY WHERE (PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:31.071 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReviewHistoryMapper.selectPage_mpCount ==> Parameters: CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:31.089 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReviewHistoryMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:31.910 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM IMPORT_TASK WHERE (STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:31.910 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount ==> Parameters: 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:31.927 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:32.138 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:32.139 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:32.156 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:32.157 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:32.157 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:32.176 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:32.176 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:32.177 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:32.193 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:32.194 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:32.194 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:32.210 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:40.350 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:40.350 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:40.368 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:40.368 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:40.368 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:40.385 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 3
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:40.385 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:40.385 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 167(Integer), 166(Integer), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:40.403 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:40.444 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:40.444 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:40.461 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:45.155 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:45.155 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:45.172 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:45.172 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:45.172 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:45.190 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:45.191 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:45.191 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:45.193 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:45.193 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:45.208 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:45.208 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:45.208 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:45.211 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:45.211 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:45.211 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:45.225 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:45.229 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.114 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.114 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 167(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.133 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.136 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.137 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.154 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.154 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.155 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.173 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.173 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.173 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.191 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.415 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.415 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.433 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.744 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.744 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.762 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.763 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.763 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:46.781 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:48.351 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:48.351 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 167(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:48.369 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:48.369 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:48.369 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:48.387 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:48.387 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:48.387 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:48.406 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:48.406 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:48.406 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:48.423 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:55.078 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:55.078 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:55.095 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:55.097 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:55.097 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:55.115 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:55.115 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage ==>  Preparing: SELECT ID,CREATE_TIME,TASK_NAME,PROGRESS,TASK_STATUS,CREATE_ID,CREATE_NAME,BEGIN_TIME,FINISH_TIME,END_TIME,TYPE,REPORT_ID,HANDLE_PERSON_ID,HANDLE_PERSON_NAME,REMARK,RESULT,SIGN_PATENT_NO FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:55.115 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage ==> Parameters: 0(Integer), 154(Integer), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:45:55.133 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:46:11.616 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:46:11.616 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:46:11.634 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:46:11.634 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:46:11.634 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:46:11.652 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:46:11.847 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:46:11.848 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:46:11.877 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:54.297 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:54.298 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:54.316 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:54.316 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:54.317 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:54.335 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:54.543 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:54.543 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:54.571 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:55.797 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:55.797 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:55.817 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:55.819 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:55.819 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:55.842 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:56.049 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:56.049 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:56.078 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:58.777 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:58.778 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:58.796 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:58.796 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:58.796 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:58.815 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:59.008 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:59.009 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:47:59.037 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 15:48:00.202 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:48:00.203 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:48:00.222 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:48:00.224 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:48:00.225 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:48:00.239 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:48:00.439 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:48:00.439 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:48:00.467 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 15:48:02.043 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:48:02.045 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:48:02.062 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:48:02.062 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:48:02.063 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:48:02.081 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:48:02.273 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:48:02.274 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:48:02.301 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:22.632 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:22.632 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:22.651 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:22.651 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:22.651 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:22.670 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 3
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:22.671 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:22.671 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 167(Integer), 166(Integer), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:22.688 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:22.710 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:22.710 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:22.728 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:28.452 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:28.452 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:28.470 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:28.471 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:28.471 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:28.489 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.057 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.057 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.077 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.077 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.077 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.096 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.096 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.096 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.112 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.112 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.112 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.134 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.134 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.134 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.154 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.154 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.154 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.162 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.162 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.162 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.192 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.192 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.192 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.210 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.210 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.210 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.230 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.230 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.230 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.246 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.246 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.246 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.269 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.384 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.385 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.414 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.414 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.414 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.429 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 9
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.429 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.429 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.445 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.735 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.735 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.754 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.756 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.756 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 41(Integer), 42(Integer), 43(Integer), 44(Integer), 45(Integer), 46(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.763 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.763 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.763 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer), 14809(Integer), 14807(Integer), 14812(Integer), 14810(Integer), 14819(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.795 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 5
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.796 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?,?,?,?,?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.797 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP1994296558A(String), JP2003093227A(String), CN102727071A(String), CN201312722Y(String), CN2258371Y(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.815 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 5
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.829 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.829 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.846 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.846 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.846 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.867 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.867 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.867 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.887 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.888 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.888 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.908 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.909 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.910 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:31.930 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:32.163 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:32.163 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:32.188 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 9
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:32.189 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:32.189 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:32.208 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:32.312 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:32.312 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:32.329 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:32.331 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:32.332 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:32.349 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:32.806 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:32.807 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:32.835 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:33.151 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:33.151 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:33.169 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:33.170 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:33.170 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 41(Integer), 42(Integer), 43(Integer), 44(Integer), 45(Integer), 46(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:33.187 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:33.189 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:33.189 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer), 14809(Integer), 14807(Integer), 14812(Integer), 14810(Integer), 14819(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:33.206 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 5
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:33.210 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?,?,?,?,?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:33.211 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP1994296558A(String), JP2003093227A(String), CN102727071A(String), CN201312722Y(String), CN2258371Y(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:33.228 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 5
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.275 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.275 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.294 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.295 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.295 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.313 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.313 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.313 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.331 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.332 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.332 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.351 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.509 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.509 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.527 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.569 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.569 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.570 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.570 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.587 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 9
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.587 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.588 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.588 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.588 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.589 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.606 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.606 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.607 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.607 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.625 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.625 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.625 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:41.643 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:47.271 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:47.271 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:47.289 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:47.289 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:47.289 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:47.307 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:47.308 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:47.308 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:47.326 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:47.328 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (CID = ? AND FID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:47.329 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: 4780(Integer), 2896(Integer), 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:47.347 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:55.872 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:55.872 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:55.887 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:55.887 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:55.887 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:55.909 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:55.909 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.TaskMapper.selectPage ==>  Preparing: SELECT ID,CREATE_TIME,TASK_NAME,PROGRESS,TASK_STATUS,CREATE_ID,CREATE_NAME,BEGIN_TIME,FINISH_TIME,END_TIME,TYPE,REPORT_ID,HANDLE_PERSON_ID,HANDLE_PERSON_NAME,REMARK,RESULT,SIGN_PATENT_NO FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:55.909 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.TaskMapper.selectPage ==> Parameters: 0(Integer), 154(Integer), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:55.928 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.TaskMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.716 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.716 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.717 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.717 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.734 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.734 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.734 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.735 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.735 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.736 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.752 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.752 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.752 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.752 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.753 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.753 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.760 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.761 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.770 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.770 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.770 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.770 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.771 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.771 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.780 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.787 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:57.788 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.323 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.323 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.340 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.341 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.347 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.347 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.348 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.358 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.359 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.359 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.365 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.366 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.366 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.376 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.376 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.376 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.384 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.384 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (CID = ? AND FID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.384 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: 4780(Integer), 2896(Integer), 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.393 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.394 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.394 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.402 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.403 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.403 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.408 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.408 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.408 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.408 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.408 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.408 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.429 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.429 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.429 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.438 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.446 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.448 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.448 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.465 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.466 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.466 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.483 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.484 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.484 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.501 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.503 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.504 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.507 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.525 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.525 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.543 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.545 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.546 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.563 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.564 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.565 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.583 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.583 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.583 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.589 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.589 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.589 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.607 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.607 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.607 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:54:58.638 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:27.098 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:27.098 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:27.116 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:27.117 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:27.117 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:27.139 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:27.139 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:27.139 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:27.157 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:33.731 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:33.731 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:33.749 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:33.750 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:33.750 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:33.767 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:33.767 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:33.767 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:33.785 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.343 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.343 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.361 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.361 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.361 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.379 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.379 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.379 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.397 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.397 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.397 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.414 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.414 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.414 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.432 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.432 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.432 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.450 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.452 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.452 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.470 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.470 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.470 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.488 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.490 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.490 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.508 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.508 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.508 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.526 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.528 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.529 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.546 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.546 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.547 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.564 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.564 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.564 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.582 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.584 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.585 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.602 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.605 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.605 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.623 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.623 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.623 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:34.641 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:41.632 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:41.633 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:41.651 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:41.655 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:41.655 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:41.673 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:41.673 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:41.673 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:41.690 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:42.929 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:42.929 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:42.948 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:42.950 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:42.950 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:42.968 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:42.969 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:42.969 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:42.988 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.564 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.564 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.582 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.582 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.582 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.600 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.601 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.601 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.618 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.618 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.618 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.635 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.635 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.635 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.653 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.654 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.654 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.671 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.673 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.673 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.690 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.691 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.691 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.708 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.708 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.709 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.726 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.726 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.726 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.744 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.744 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.744 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.762 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.764 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.765 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.782 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.784 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.785 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.803 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.806 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.806 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.824 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.825 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.825 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.841 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.842 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.842 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:43.859 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:47.256 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:47.257 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:47.274 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:47.274 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:47.274 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:47.292 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:47.292 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:47.292 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:47.310 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:47.310 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (CID = ? AND FID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:47.310 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: 4780(Integer), 2896(Integer), 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:47.328 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:47.328 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:47.328 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:47.346 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:47.346 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:47.346 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:47.363 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.311 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.311 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.329 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.330 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (CID = ? AND FID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.330 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: 4780(Integer), 2896(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.348 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.348 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.348 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.369 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.369 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.369 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.390 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.891 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.891 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.909 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.909 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.910 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.930 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.930 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.930 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.951 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.951 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.951 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.972 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.972 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.972 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:50.990 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:52.716 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:52.716 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:52.727 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:52.727 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (CID = ? AND FID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:52.727 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: 4780(Integer), 2896(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:52.752 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:52.753 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (CID = ? AND FID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:52.753 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: 4780(Integer), 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:52.771 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 3
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:52.771 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:52.771 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:52.789 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:52.789 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:52.789 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:52.808 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.231 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.231 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.248 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.249 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.249 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.267 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.267 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.267 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.285 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.845 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.845 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.863 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.863 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.863 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.880 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.880 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.880 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.898 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.899 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.899 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.916 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.917 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.917 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.934 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.934 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.934 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.952 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.953 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.954 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.962 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.962 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.962 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.989 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.989 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:54.989 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.007 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.007 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.007 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.024 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.025 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.025 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.042 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.043 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.043 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.061 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.064 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.065 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.082 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.084 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.084 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.103 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.105 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.105 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.122 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.122 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.123 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:55:55.140 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:38.507 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TYPE = ? AND TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:38.507 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 2(Integer), 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:38.524 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:38.525 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TYPE = ? AND TASK_STATUS = ? AND HANDLE_PERSON_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:38.525 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 2(Integer), 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:38.543 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:38.543 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectPage ==>  Preparing: SELECT ID,CREATE_TIME,TASK_NAME,PROGRESS,TASK_STATUS,CREATE_ID,CREATE_NAME,BEGIN_TIME,FINISH_TIME,END_TIME,TYPE,REPORT_ID,HANDLE_PERSON_ID,HANDLE_PERSON_NAME,REMARK,RESULT,SIGN_PATENT_NO FROM TASK WHERE (TYPE = ? AND TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:38.543 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectPage ==> Parameters: 2(Integer), 0(Integer), 154(Integer), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:38.561 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.TaskMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:41.680 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TYPE = ? AND TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:41.680 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:41.698 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:41.699 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TYPE = ? AND TASK_STATUS = ? AND HANDLE_PERSON_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:41.699 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:41.716 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:45.279 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND CREATE_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:45.279 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:45.302 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:45.303 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND CREATE_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:45.304 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:45.321 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:46.667 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:46.667 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:46.684 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:46.684 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:46.684 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:46.702 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 3
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:46.702 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:46.703 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 167(Integer), 166(Integer), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:46.720 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:46.740 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:46.741 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:46.758 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:49.940 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:49.940 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:49.958 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:49.963 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:49.963 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount ==> Parameters: 0(Integer), 154(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:49.980 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:49.980 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectPage ==>  Preparing: SELECT ID,CREATE_TIME,TASK_NAME,PROGRESS,TASK_STATUS,CREATE_ID,CREATE_NAME,BEGIN_TIME,FINISH_TIME,END_TIME,TYPE,REPORT_ID,HANDLE_PERSON_ID,HANDLE_PERSON_NAME,REMARK,RESULT,SIGN_PATENT_NO FROM TASK WHERE (TASK_STATUS = ? AND HANDLE_PERSON_ID = ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:49.980 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectPage ==> Parameters: 0(Integer), 154(Integer), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:49.998 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.TaskMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.237 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.237 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.265 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.265 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.265 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.269 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.269 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.283 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.284 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.284 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.285 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.285 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.289 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.302 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.303 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.304 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.304 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.305 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.305 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.306 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.306 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.320 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.320 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.320 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.320 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.320 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.342 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.886 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.886 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.905 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.905 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.905 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.935 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.935 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.935 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.953 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.954 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.954 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.972 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.972 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.972 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.987 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.987 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:52.987 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.009 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.014 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.014 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: KR1020160016352A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.032 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.033 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.033 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.051 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.052 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.052 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.070 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.074 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.074 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.093 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.095 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.095 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4784(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.112 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.113 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.113 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: US20110256287A1(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.131 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.133 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (ID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.133 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.151 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.151 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.151 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.170 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.170 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID IN (?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.170 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.188 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.188 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId,SID AS parentId,ZID AS treeId,LEVEL,`ORDER`,PATH,REPORT_ID FROM OS_PATENT_FIELD_TREE WHERE (CID IN (?,?)) ORDER BY `ORDER` ASC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.189 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList ==> Parameters: 4780(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:53.206 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTreeMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:54.922 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:54.922 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:54.943 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:55.085 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:55.085 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:55.102 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:55.102 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:55.103 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:55.103 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:55.103 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:55.121 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:55.121 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:55.122 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:55.122 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:55.141 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:55.142 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:55.142 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:55.159 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:56.000 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:56.000 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:56.027 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:56.027 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:56.027 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:56.040 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:56.040 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:56.040 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:56.064 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:56.064 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:56.064 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:56:56.082 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.474 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.474 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.492 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.492 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.493 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.511 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.710 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.710 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.727 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.727 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.738 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.746 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.746 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.746 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.761 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.761 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.761 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.785 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.785 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.785 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.789 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.789 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.804 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:00.807 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.566 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.566 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.584 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.865 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.865 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.881 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.881 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.881 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.881 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.898 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.899 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.899 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer), 4780(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.900 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.900 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.916 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.918 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.918 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 2897(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.936 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.936 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==>  Preparing: SELECT ID,FID AS optionId,CID AS fieldId,TYPE,PATENT_NO,REPORT_ID,USER_ID AS createBy FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.936 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:04.949 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:08.129 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:08.129 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: JP2003093227A(String), 166(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:08.164 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:08.165 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:08.165 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:08.182 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:11.612 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (PATENT_NO = ? AND REPORT_ID = ? AND CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:11.612 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: JP2003093227A(String), 166(Integer), 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:11.648 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:11.648 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==>  Preparing: SELECT ID,NAME AS text,CID AS fieldId FROM OS_PATENT_FIELD_TEXT WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:11.648 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList ==> Parameters: 4784(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:11.666 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldTextMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:34.003 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:34.003 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:34.021 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:34.021 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:34.022 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:34.040 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 3
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:34.040 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:34.040 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 167(Integer), 166(Integer), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:34.058 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:34.080 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:34.080 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:34.098 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:37.769 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:37.769 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==> Parameters: 166(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:37.788 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:37.788 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:37.788 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==> Parameters: 166(Integer), %%(String), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:37.806 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectPage <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:37.806 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:37.807 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==> Parameters: 166(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:37.825 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:56.899 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:56.899 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:56.917 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:56.918 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:56.918 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:56.936 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:56.937 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:56.937 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:56.955 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:56.955 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:56.955 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:56.973 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.145 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.145 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.163 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.208 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.208 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.208 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.208 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.226 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.226 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.226 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.228 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 9
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.228 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.228 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.245 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.245 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.245 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.246 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.263 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.263 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.263 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:57.281 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:58.652 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:58.652 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:58.669 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:58.669 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:58.669 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:58.687 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:58.688 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:58.688 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:58.706 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:58.706 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:58.706 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:57:58.724 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:58:21.223 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:58:21.224 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 166(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:58:21.242 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 15:58:21.243 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:58:21.243 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:58:21.261 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 15:58:21.262 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:58:21.262 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:58:21.280 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 15:58:21.280 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 15:58:21.280 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 15:58:21.299 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:01:43.627 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:01:43.627 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:01:43.646 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:01:43.647 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:01:43.647 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:01:43.665 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:01:43.878 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:01:43.878 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:01:43.906 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:02:09.297 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFileMapper.insert ==>  Preparing: INSERT INTO REPORT_FILE ( NAME, FILE_NAME, ADDRESS, UID, SIZE, SUFFIX ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 16:02:09.297 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFileMapper.insert ==> Parameters: 容器(String), 814281b1f7884129b06b387b22d33e79.svg(String), \20221212\814281b1f7884129b06b387b22d33e79.svg(String), 154(Integer), 1639(Integer), svg(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:02:09.336 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.insert ==>  Preparing: INSERT INTO COMPARE_RECORDS ( PATENT_NO, POSITION, FIELDS, CONTENT, FILE_PATH, REPORT_ID, TASK_ID ) VALUES ( ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 16:02:09.338 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.insert ==> Parameters: CN109924892B(String), 61(String), 摘要(String), ，顶部与承载部形(String), \20221212\814281b1f7884129b06b387b22d33e79.svg(String), 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:02:09.374 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:02:59.638 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:02:59.638 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:02:59.657 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:02:59.658 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:02:59.658 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:02:59.677 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:02:59.887 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:02:59.887 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:02:59.917 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:03:01.041 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:03:01.042 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:03:01.060 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:03:01.060 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:03:01.061 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:03:01.079 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:03:01.272 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:03:01.272 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:03:01.301 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:56.535 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:56.535 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:56.553 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:56.553 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:56.554 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:56.572 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:56.572 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:56.572 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:56.590 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:56.590 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:56.590 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:56.609 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:57.139 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:57.141 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:57.159 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:57.160 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:57.160 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:57.177 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:57.177 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:57.177 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:57.190 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:57.190 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:57.190 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:57.206 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:57.514 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:57.514 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:57.532 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:57.554 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:57.554 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:06:57.572 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:02.852 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:02.852 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:02.869 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:02.869 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:02.869 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:02.886 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:03.077 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:03.077 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:03.104 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:17.521 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:17.521 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:17.521 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:17.522 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:17.537 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:17.537 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:17.537 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:17.539 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:17.554 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:17.554 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:17.554 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:17.559 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:17.559 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:17.571 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:17.571 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:17.571 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:17.577 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:17.587 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:18.094 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:18.094 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:18.111 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:18.112 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:18.112 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:18.127 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:18.127 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:18.127 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:18.148 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:18.151 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:18.151 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:18.167 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:21.917 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:21.917 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:21.934 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:21.934 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:21.934 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:21.951 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:22.140 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:22.140 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:07:22.167 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:35.284 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:35.284 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:35.302 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:35.368 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:35.368 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:35.386 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:36.051 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:36.051 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:36.067 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:36.068 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:36.068 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:36.091 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:36.091 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:36.091 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:36.129 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:36.131 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:36.131 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:36.148 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:38.620 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:38.620 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:38.638 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:38.638 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:38.638 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:38.645 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:38.645 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:38.645 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:38.674 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:38.674 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:38.674 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:38.692 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:42.946 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:42.946 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:42.964 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.233 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.233 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.250 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.251 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.251 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.252 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.252 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.268 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.269 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.269 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.269 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.287 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.287 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.287 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.304 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.904 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.904 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.922 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.922 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.922 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.939 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.939 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.939 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.956 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.957 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.957 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:15:43.975 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:06.979 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:06.980 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.066 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.066 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.066 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.082 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.083 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.084 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.084 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.085 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.100 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.101 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.102 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.103 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.119 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.120 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.120 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.137 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.803 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.803 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.822 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.822 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.822 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.841 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.844 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.844 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.861 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.861 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.861 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:07.881 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:12.918 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:12.918 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:12.936 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:12.936 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:12.936 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:12.953 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:13.144 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:13.144 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:16:13.171 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:03.835 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:03.835 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:03.854 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:03.854 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:03.854 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:03.871 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:04.067 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:04.067 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:04.095 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:33.084 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:33.084 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:33.100 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:33.100 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:33.100 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:33.131 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:33.322 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:33.322 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:33.338 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:35.737 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:35.737 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:35.753 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:35.753 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:35.753 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:35.784 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:35.969 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:35.969 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:36.006 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:43.884 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:43.884 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:43.886 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:43.902 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:43.902 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:43.902 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:43.902 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:43.918 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:43.918 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:43.918 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:43.918 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:43.918 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:43.918 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:43.933 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:43.933 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:43.933 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:43.933 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:43.950 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:44.509 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:44.509 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:44.525 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:44.526 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:44.526 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:44.543 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:44.543 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:44.543 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:44.561 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:44.561 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:44.561 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:44.578 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:47.143 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:47.144 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:47.162 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:47.162 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:47.162 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:47.180 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:47.379 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:47.379 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:17:47.407 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:18:03.470 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:18:03.470 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:18:03.488 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:18:03.488 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:18:03.488 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:18:03.505 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:18:03.696 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:18:03.696 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:18:03.723 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:27.878 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:27.878 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:27.895 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:27.895 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:27.895 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:27.913 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:28.127 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:28.127 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:28.153 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:29.514 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:29.514 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:29.533 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:29.535 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:29.535 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:29.552 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:29.742 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:29.742 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:29.770 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:35.499 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:35.500 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:35.518 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:35.519 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:35.520 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:35.537 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:35.727 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:35.728 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:35.755 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:39.754 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:39.755 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:39.772 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:39.772 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:39.772 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:39.790 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:39.989 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:39.989 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:40.016 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:41.705 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:41.705 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:41.723 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:41.725 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:41.725 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:41.743 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:41.948 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:41.949 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:41.976 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.398 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.398 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.415 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.415 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.415 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.419 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.420 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.432 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.433 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.433 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.438 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.450 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.452 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.452 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.462 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.462 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.470 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.480 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.993 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:48.993 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:49.011 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:49.011 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:49.011 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:49.028 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:49.028 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:49.028 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:49.046 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:49.046 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:49.046 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:49.063 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:53.492 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:53.493 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:53.511 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:53.511 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:53.511 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:53.528 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:53.728 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:53.728 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:25:53.755 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:49.725 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:49.726 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:49.744 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:49.745 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:49.746 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:49.764 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:49.956 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:49.957 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:49.984 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:53.570 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:53.571 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:53.588 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:53.588 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:53.588 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:53.606 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:53.794 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:53.794 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:53.822 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:55.426 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:55.426 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:55.443 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:55.443 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:55.443 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:55.461 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:55.659 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:55.659 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:55.686 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:59.624 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:59.624 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:59.642 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:59.642 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:59.643 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:59.660 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:59.847 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:59.848 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:26:59.876 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:00.985 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:00.985 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:01.002 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:01.002 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:01.002 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:01.021 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:01.213 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:01.213 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:01.240 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:22.965 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:22.965 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:22.982 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:22.982 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:22.982 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:22.984 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:22.985 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:22.999 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:22.999 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:22.999 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.001 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.004 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.004 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.016 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.017 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.017 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.022 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.034 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.549 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.549 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.566 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.566 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.567 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.583 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.583 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.583 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.601 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.601 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.601 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:23.618 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:26.824 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:26.824 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:26.842 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:26.842 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:26.843 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:26.860 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:27.050 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:27.050 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:27:27.078 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:30:15.879 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:30:15.879 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:30:15.898 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:30:15.898 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:30:15.898 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:30:15.915 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:30:16.146 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:30:16.146 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:30:16.174 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:31:15.761 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFileMapper.insert ==>  Preparing: INSERT INTO REPORT_FILE ( NAME, FILE_NAME, ADDRESS, UID, SIZE, SUFFIX ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 16:31:15.761 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFileMapper.insert ==> Parameters: 容器(String), c92b2b48b6174ded9e00f06ced8a9d39.png(String), \20221212\c92b2b48b6174ded9e00f06ced8a9d39.png(String), 154(Integer), 4735(Integer), png(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:31:15.796 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.insert ==>  Preparing: INSERT INTO COMPARE_RECORDS ( PATENT_NO, POSITION, FIELDS, CONTENT, FILE_PATH, REPORT_ID, TASK_ID ) VALUES ( ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 16:31:15.797 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.insert ==> Parameters: JP2003093227A(String), 30(String), 摘要(String), 与煮饭量对应的水分,(String), \20221212\c92b2b48b6174ded9e00f06ced8a9d39.png(String), 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:31:15.831 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:33.971 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:33.971 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:33.989 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:34.120 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:34.120 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:34.138 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:34.595 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:34.595 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:34.613 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:34.613 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:34.613 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:34.631 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:34.631 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:34.631 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:34.648 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:34.648 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:34.649 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:34.666 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:36.241 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:36.242 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:36.259 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:36.568 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:36.568 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:36.585 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:37.527 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:37.527 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:37.545 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:37.545 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:37.545 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:37.563 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:37.565 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:37.565 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:37.582 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:37.583 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:37.583 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:37.600 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:37.923 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:37.923 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:37.941 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:38.248 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:38.248 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:38.266 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:38.840 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:38.840 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:38.858 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:38.858 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:38.858 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:38.875 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:38.877 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:38.877 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:38.895 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:38.899 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:38.899 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:38.917 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:42.550 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:42.551 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:42.568 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:42.572 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:42.572 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:42.589 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:42.590 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:42.590 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:42.612 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:42.615 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:42.615 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:42.632 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:42.634 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:42.634 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:42.652 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:43.168 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:43.168 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:43.185 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:43.186 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:43.186 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:43.203 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:43.205 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:43.205 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:43.223 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:43.225 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:43.225 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:43.243 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:43.615 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:43.615 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:43.632 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:52.209 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:52.209 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:59.497 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFileMapper.insert ==>  Preparing: INSERT INTO REPORT_FILE ( NAME, FILE_NAME, ADDRESS, UID, SIZE, SUFFIX ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:59.497 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFileMapper.insert ==> Parameters: 容器(String), cb6c67ba23704a47a0f4982d772592c1.png(String), \20221212\cb6c67ba23704a47a0f4982d772592c1.png(String), 154(Integer), 4735(Integer), png(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:59.532 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.insert ==>  Preparing: INSERT INTO COMPARE_RECORDS ( PATENT_NO, POSITION, FIELDS, CONTENT, FILE_PATH, REPORT_ID, TASK_ID ) VALUES ( ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:59.532 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.insert ==> Parameters: JP2003093227A(String), 42(String), 摘要(String), 米煮出之(String), \20221212\cb6c67ba23704a47a0f4982d772592c1.png(String), 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:35:59.565 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:02.472 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:02.473 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:02.491 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:02.493 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:02.493 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:02.511 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:02.714 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:02.714 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:02.741 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:52.664 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:52.665 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:52.683 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:52.832 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:52.833 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:52.850 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:53.263 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:53.263 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:53.280 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:53.280 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:53.280 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:53.298 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:53.298 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:53.298 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:53.315 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:53.316 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:53.316 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:53.333 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:56.954 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:56.955 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:56.957 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:56.958 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:56.973 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:56.975 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:56.975 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:56.975 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:56.992 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:56.993 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:56.993 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:56.996 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:56.997 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:57.010 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:57.011 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:57.011 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:57.014 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:57.027 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:57.539 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:57.539 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:57.556 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:57.556 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:57.556 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:57.574 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:57.574 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:57.574 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:57.591 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:57.591 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:57.592 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:36:57.609 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:01.580 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:01.581 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:01.599 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:01.599 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:01.599 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:01.617 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:01.808 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:01.808 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:01.836 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:19.282 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFileMapper.insert ==>  Preparing: INSERT INTO REPORT_FILE ( NAME, FILE_NAME, ADDRESS, UID, SIZE, SUFFIX ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:19.282 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFileMapper.insert ==> Parameters: 容器(String), ffb3866835be4e87b82dc140e5a62150.png(String), \20221212\ffb3866835be4e87b82dc140e5a62150.png(String), 154(Integer), 4735(Integer), png(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:19.317 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.insert ==>  Preparing: INSERT INTO COMPARE_RECORDS ( PATENT_NO, POSITION, FIELDS, CONTENT, FILE_PATH, REPORT_ID, TASK_ID ) VALUES ( ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:19.317 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.insert ==> Parameters: JP2003093227A(String), 31(String), 摘要(String), 煮饭量对应(String), \20221212\ffb3866835be4e87b82dc140e5a62150.png(String), 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:19.350 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:22.465 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:22.465 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:22.483 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:22.485 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:22.486 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:22.503 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:22.697 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:22.698 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:37:22.725 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:11.669 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:11.670 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:11.687 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:11.932 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:11.932 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:11.949 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:12.495 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:12.496 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:12.513 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:12.513 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:12.513 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:12.531 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:12.533 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:12.533 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:12.550 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:12.551 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:12.551 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:12.569 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:15.299 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:15.299 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:15.317 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:15.551 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:15.551 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:15.568 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:16.110 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:16.110 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:16.127 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:16.127 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:16.127 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:16.143 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:16.144 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:16.144 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:16.161 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:16.161 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:16.161 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:16.179 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:30.920 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:30.921 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:30.938 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:30.938 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:30.939 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:30.943 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:30.943 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:30.955 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:30.955 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:30.955 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:30.960 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:30.973 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:30.975 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:30.975 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:30.992 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:31.510 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:31.511 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:31.528 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:31.528 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:31.528 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:31.546 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:31.548 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:31.548 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:31.565 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:31.565 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:31.565 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:31.582 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:31.956 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:31.956 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:31.973 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:35.446 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:35.446 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:35.463 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:35.463 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:35.463 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:35.480 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:35.668 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:35.668 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:35.696 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:43.904 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFileMapper.insert ==>  Preparing: INSERT INTO REPORT_FILE ( NAME, FILE_NAME, ADDRESS, UID, SIZE, SUFFIX ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:43.904 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFileMapper.insert ==> Parameters: 容器(String), 299679e736b74214b811b69b3a963a13.png(String), \20221212\299679e736b74214b811b69b3a963a13.png(String), 154(Integer), 4735(Integer), png(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:43.938 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.insert ==>  Preparing: INSERT INTO COMPARE_RECORDS ( PATENT_NO, POSITION, FIELDS, CONTENT, FILE_PATH, REPORT_ID, TASK_ID ) VALUES ( ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:43.939 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.insert ==> Parameters: JP2003093227A(String), 40(String), 摘要(String), 免洗米(String), \20221212\299679e736b74214b811b69b3a963a13.png(String), 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:38:43.972 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:41:18.224 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:41:18.224 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:41:18.241 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:41:18.390 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:41:18.390 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:41:18.406 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:41:18.808 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:41:18.808 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:41:18.825 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:41:18.825 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:41:18.825 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:41:18.842 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:41:18.844 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:41:18.844 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:41:18.862 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:41:18.864 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:41:18.865 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:41:18.881 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:40.798 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:40.798 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:40.815 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:40.973 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:40.973 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:40.990 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:41.410 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:41.410 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:41.427 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:41.427 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:41.427 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:41.444 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:41.444 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:41.444 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:41.461 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:41.461 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:41.462 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:41.478 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:43.015 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:43.016 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:43.033 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:43.061 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:43.062 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:43.078 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:43.626 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:43.627 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:43.647 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:43.647 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:43.647 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:43.664 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:43.665 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:43.665 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:43.681 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:43.684 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:43.684 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:43.702 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:44.022 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:44.023 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:44.040 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:44.042 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:44.043 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:44.059 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:44.060 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:44.060 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:44.077 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:44.077 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:44.077 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:44.094 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:46.559 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:46.559 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:46.578 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:46.580 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:46.580 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:46.599 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:46.794 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:46.794 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:47:46.822 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:20.400 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:20.400 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:20.418 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:20.587 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:20.587 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:20.605 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:20.998 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:20.999 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:21.017 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:21.017 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:21.017 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:21.034 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:21.036 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:21.036 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:21.054 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:21.054 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:21.054 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:21.072 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.367 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.367 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.385 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.385 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.385 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.386 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.386 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.402 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.403 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.406 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.406 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.406 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.407 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.424 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.425 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.425 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.427 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.443 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.961 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.962 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.979 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.981 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.981 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:24.999 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:25.000 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:25.000 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:25.017 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:25.017 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:25.017 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:25.035 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:27.435 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:27.435 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:27.453 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:27.453 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:27.453 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:27.471 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:27.669 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:27.670 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:27.697 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:54.096 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:54.096 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:54.114 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:54.338 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:54.338 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:54.355 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:55.164 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:55.165 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:55.186 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:55.189 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:55.189 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:55.207 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:55.209 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:55.210 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:55.229 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:55.230 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:55.230 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:55.249 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:55.261 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:55.262 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:55.279 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:55.535 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:55.535 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:55.553 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:56.097 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:56.097 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:56.115 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:56.115 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:56.115 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:56.133 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:56.133 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:56.133 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:56.151 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:56.153 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:56.154 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:49:56.171 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:52:53.165 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:52:53.166 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:52:53.184 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:52:53.186 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:52:53.186 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:52:53.204 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 16:52:53.425 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:52:53.425 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 16:52:53.454 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 17:00:09.997 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFileMapper.insert ==>  Preparing: INSERT INTO REPORT_FILE ( NAME, FILE_NAME, ADDRESS, UID, SIZE, SUFFIX ) VALUES ( ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 17:00:09.998 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFileMapper.insert ==> Parameters: 容器(String), 1aa2bfdcaf7c4d2b8b11d41f8c81f4da.png(String), \20221212\1aa2bfdcaf7c4d2b8b11d41f8c81f4da.png(String), 154(Integer), 4735(Integer), png(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:00:09.998 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFileMapper.insert ==> Parameters: OIP-C(String), 565aac15aa6d4e26865b3ddd0c704a05.jpg(String), \20221212\565aac15aa6d4e26865b3ddd0c704a05.jpg(String), 154(Integer), 29574(Integer), jpg(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:00:10.057 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.insert ==>  Preparing: INSERT INTO COMPARE_RECORDS ( PATENT_NO, POSITION, FIELDS, CONTENT, FILE_PATH, REPORT_ID, TASK_ID ) VALUES ( ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 17:00:10.058 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.insert ==> Parameters: JP2003093227A(String), 40(String), 摘要(String), 免洗米煮出之前(String), \20221212\1aa2bfdcaf7c4d2b8b11d41f8c81f4da.png(String), 166(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:00:10.096 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareRecordsMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.258 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.delete ==>  Preparing: DELETE FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.258 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.delete ==> Parameters: 52(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.296 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.delete <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.300 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.insert ==>  Preparing: INSERT INTO ASSO_RECORDS_FEATURES ( ID, RECORDS_ID, FEATURE_ID ) VALUES ( ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.301 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.insert ==> Parameters: 24185(Integer), 52(Integer), 24185(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.346 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.updateById ==>  Preparing: UPDATE COMPARE_RECORDS SET PATENT_NO=?, POSITION=?, FIELDS=?, CONTENT=?, REPORT_ID=?, TASK_ID=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.346 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.updateById ==> Parameters: CN102522896B(String), 26(String), 摘要(String), 所述并联连接的谐振转换器电路，(String), 167(Integer), 145(Integer), 52(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.384 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.578 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.578 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 167(Integer), CN102522896B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.597 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.597 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.598 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.598 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.598 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 52(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.614 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.614 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.614 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.617 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.617 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.617 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 24185(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.631 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.636 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.636 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.636 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102522896B(String), 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:08.656 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:10.494 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:10.494 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:10.552 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:10.553 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:10.554 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:10.578 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:11.373 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:11.373 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:11.443 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 154
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:11.904 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:11.904 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:05:11.945 DEBUG 4308 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 154
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:52.364 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:52.364 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:52.383 DEBUG 4308 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:52.495 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:52.496 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:52.515 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:52.516 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:52.516 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:52.532 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:52.532 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:52.535 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:52.536 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:52.536 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:52.548 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:52.555 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:52.556 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:52.556 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:52.575 DEBUG 4308 [http-nio-8885-exec-2] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:53.521 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:53.521 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:53.539 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:53.540 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:53.540 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:53.559 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:53.559 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:53.559 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:53.579 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:53.579 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:53.579 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:53.599 DEBUG 4308 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:54.809 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReviewHistoryMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REVIEW_HISTORY WHERE (PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:54.809 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReviewHistoryMapper.selectPage_mpCount ==> Parameters: CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:06:54.829 DEBUG 4308 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReviewHistoryMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:00.445 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:00.445 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:00.446 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:00.447 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:00.462 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:00.463 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:00.463 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:00.466 DEBUG 4308 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:00.466 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:00.466 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:00.479 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:00.480 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:00.480 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:00.485 DEBUG 4308 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:00.496 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:00.497 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:00.497 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:00.513 DEBUG 4308 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:02.792 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:02.792 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:02.809 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:02.809 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:02.809 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:02.826 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:02.828 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:02.829 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:02.846 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:02.848 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:02.848 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:02.866 DEBUG 4308 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:09.052 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:09.053 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:09.070 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:09.071 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:09.071 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:09.088 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:09.279 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:09.279 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:09:09.306 DEBUG 4308 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 17:11:43.279 DEBUG 10280 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM OS_PATENT_FIELD WHERE (NAME LIKE ? AND REPORT_TYPE LIKE ? AND REPORT_ID IS NULL)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:11:43.304 DEBUG 10280 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==> Parameters: %%(String), %0%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:11:43.338 DEBUG 10280 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:11:43.342 DEBUG 10280 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (NAME LIKE ? AND REPORT_TYPE LIKE ? AND REPORT_ID IS NULL) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:11:43.343 DEBUG 10280 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==> Parameters: %%(String), %0%(String), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:11:43.363 DEBUG 10280 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:11:43.364 DEBUG 10280 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM OS_PATENT_FIELD WHERE (NAME LIKE ? AND REPORT_TYPE LIKE ? AND REPORT_ID IS NULL) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 17:11:43.365 DEBUG 10280 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==> Parameters: %%(String), %0%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:11:43.382 DEBUG 10280 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:11:52.752 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:11:52.753 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:11:52.772 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:11:52.773 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:11:52.774 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:11:52.792 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:11:53.118 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:11:53.119 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:11:53.150 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 17:12:16.716 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.insert ==>  Preparing: INSERT INTO REPORT ( SIGN_PATENT_NO, NAME, TYPE, STATUS, PERSON_ID, PERSON_NAME, CLIENT_ID, CLIENT_NAME, DEPARTMENT_ID, DEPARTMENT_NAME, CREATE_PERSON_ID, CREATE_PERSON_NAME ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 17:12:16.717 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.insert ==> Parameters: JP2003093227A(String), JP2003093227A无效分析(String), 0(Integer), 1(Integer), 154(Integer), 朱豪(String), 30(Integer), 星际悦动(String), 58(Integer), syy(String), 154(Integer), 朱豪(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:12:16.751 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:12:16.755 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_TYPE = ? AND REPORT_ID IS NULL)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:12:16.755 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:12:16.774 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:12:16.788 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD ( NAME, PTYPE, TYPE, STATUS, REMARK, CID, CREATE_TIME, REPORT_ID, REPORT_TYPE ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 17:12:16.791 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.insert ==> Parameters: 相关性(String), 1(Integer), 5(Integer), 1(Integer), (String), 114(Integer), 2022-12-12 10:19:53.0(Timestamp), 172(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.827 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.827 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.846 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.847 DEBUG 10280 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.848 DEBUG 10280 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 167(Integer), CN102522896B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.865 DEBUG 10280 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.866 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.866 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.883 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.883 DEBUG 10280 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.884 DEBUG 10280 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 52(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.902 DEBUG 10280 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.902 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.903 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.920 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.921 DEBUG 10280 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.921 DEBUG 10280 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 24185(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.938 DEBUG 10280 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.940 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.941 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.957 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.958 DEBUG 10280 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.958 DEBUG 10280 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102522896B(String), 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:20.976 DEBUG 10280 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.170 DEBUG 10280 [http-nio-8885-exec-12] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.170 DEBUG 10280 [http-nio-8885-exec-12] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.181 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.181 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.188 DEBUG 10280 [http-nio-8885-exec-12] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.190 DEBUG 10280 [http-nio-8885-exec-12] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.190 DEBUG 10280 [http-nio-8885-exec-12] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.199 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.200 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.200 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.208 DEBUG 10280 [http-nio-8885-exec-12] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.210 DEBUG 10280 [http-nio-8885-exec-12] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.210 DEBUG 10280 [http-nio-8885-exec-12] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.218 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.227 DEBUG 10280 [http-nio-8885-exec-12] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.228 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.228 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 172(Integer), 170(Integer), 169(Integer), 168(Integer), 167(Integer), 166(Integer), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.228 DEBUG 10280 [http-nio-8885-exec-12] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.229 DEBUG 10280 [http-nio-8885-exec-12] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.245 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.246 DEBUG 10280 [http-nio-8885-exec-12] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.270 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.271 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:21.288 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.429 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.429 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.430 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.431 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 167(Integer), CN102522896B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.448 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.449 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.449 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.449 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.450 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.450 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 52(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.466 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.466 DEBUG 10280 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.467 DEBUG 10280 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 114(Integer), 145(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.467 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.467 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.468 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.483 DEBUG 10280 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.483 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.484 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 24185(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.484 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.485 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.486 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.502 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.505 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.508 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.509 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102522896B(String), 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:22.527 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:23.119 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:23.119 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 167(Integer), CN102522896B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:23.137 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:23.138 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:23.138 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 52(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:23.155 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:23.156 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:23.156 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 24185(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:23.174 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:23.176 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:23.176 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102522896B(String), 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:13:23.192 DEBUG 10280 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:12.894 DEBUG 10280 [http-nio-8885-exec-13] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:12.894 DEBUG 10280 [http-nio-8885-exec-13] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:12.894 DEBUG 10280 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:12.895 DEBUG 10280 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:12.911 DEBUG 10280 [http-nio-8885-exec-13] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:12.913 DEBUG 10280 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:12.913 DEBUG 10280 [http-nio-8885-exec-13] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:12.913 DEBUG 10280 [http-nio-8885-exec-13] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:12.930 DEBUG 10280 [http-nio-8885-exec-13] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:12.931 DEBUG 10280 [http-nio-8885-exec-13] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:12.931 DEBUG 10280 [http-nio-8885-exec-13] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:12.934 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:12.934 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:12.949 DEBUG 10280 [http-nio-8885-exec-13] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:12.950 DEBUG 10280 [http-nio-8885-exec-13] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:12.950 DEBUG 10280 [http-nio-8885-exec-13] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:12.967 DEBUG 10280 [http-nio-8885-exec-13] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:13.413 DEBUG 10280 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:13.897 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:13.897 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:13.914 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:13.915 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:13.915 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:13.932 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:13.933 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:13.933 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:13.950 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:13.952 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:13.952 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:13.969 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.704 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.704 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.721 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.721 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.722 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.726 DEBUG 10280 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.726 DEBUG 10280 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.742 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.743 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.744 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 172(Integer), 170(Integer), 169(Integer), 168(Integer), 167(Integer), 166(Integer), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.744 DEBUG 10280 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.745 DEBUG 10280 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.745 DEBUG 10280 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.760 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.761 DEBUG 10280 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.763 DEBUG 10280 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.763 DEBUG 10280 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.780 DEBUG 10280 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.781 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.781 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.781 DEBUG 10280 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.781 DEBUG 10280 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.799 DEBUG 10280 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:24.799 DEBUG 10280 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:53.816 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.insert ==>  Preparing: INSERT INTO REPORT ( SIGN_PATENT_NO, NAME, TYPE, STATUS, PERSON_ID, PERSON_NAME, CLIENT_ID, CLIENT_NAME, DEPARTMENT_ID, DEPARTMENT_NAME, SCENARIO_ID, CREATE_PERSON_ID, CREATE_PERSON_NAME ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:53.818 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.insert ==> Parameters: JP2003093227A(String), JP2003093227A无效分析(String), 0(Integer), 1(Integer), 135(Integer), 测试9(String), 28(Integer), 美的集团(String), 58(Integer), syy(String), (String), 154(Integer), 朱豪(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:53.851 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:53.855 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_TYPE = ? AND REPORT_ID IS NULL)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:53.856 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:53.875 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:53.878 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD ( NAME, PTYPE, TYPE, STATUS, REMARK, CID, CREATE_TIME, REPORT_ID, REPORT_TYPE ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 17:14:53.880 DEBUG 10280 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.insert ==> Parameters: 相关性(String), 1(Integer), 5(Integer), 1(Integer), (String), 114(Integer), 2022-12-12 10:19:53.0(Timestamp), 173(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.609 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.632 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.676 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.729 DEBUG 5500 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.729 DEBUG 5500 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.746 DEBUG 5500 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.749 DEBUG 5500 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.750 DEBUG 5500 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.771 DEBUG 5500 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.779 DEBUG 5500 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.780 DEBUG 5500 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 173(Integer), 172(Integer), 170(Integer), 169(Integer), 168(Integer), 167(Integer), 166(Integer), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.797 DEBUG 5500 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.817 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.819 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.828 DEBUG 5500 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.828 DEBUG 5500 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.839 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.840 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.841 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.845 DEBUG 5500 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.860 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.861 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.862 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:19.881 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:35.738 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.insert ==>  Preparing: INSERT INTO REPORT ( SIGN_PATENT_NO, NAME, TYPE, STATUS, PERSON_ID, PERSON_NAME, CLIENT_ID, CLIENT_NAME, DEPARTMENT_ID, DEPARTMENT_NAME, SCENARIO_ID, CREATE_PERSON_ID, CREATE_PERSON_NAME ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:35.739 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.insert ==> Parameters: JP2003093227A(String), JP2003093227A无效分析(String), 0(Integer), 1(Integer), 154(Integer), 朱豪(String), 30(Integer), 星际悦动(String), 58(Integer), syy(String), (String), 154(Integer), 朱豪(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:35.777 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:35.787 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_TYPE = ? AND REPORT_ID IS NULL)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:35.787 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:35.807 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:35.812 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD ( NAME, PTYPE, TYPE, STATUS, REMARK, CID, CREATE_TIME, REPORT_ID, REPORT_TYPE ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 17:17:35.815 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.insert ==> Parameters: 相关性(String), 1(Integer), 5(Integer), 1(Integer), (String), 114(Integer), 2022-12-12 10:19:53.0(Timestamp), 174(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:18:02.090 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:18:02.093 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4793(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:18:02.119 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:13.846 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:13.847 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:13.857 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:13.857 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:13.867 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:13.868 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:13.868 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:13.875 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:13.877 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:13.877 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:13.894 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:13.896 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:13.896 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:13.914 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:13.915 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:13.916 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:13.933 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:14.223 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 9
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:14.225 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?,?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:14.226 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 174(Integer), 173(Integer), 172(Integer), 170(Integer), 169(Integer), 168(Integer), 167(Integer), 166(Integer), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:14.245 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:14.275 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:14.276 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:14.296 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:17.928 DEBUG 5500 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:17.928 DEBUG 5500 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:17.948 DEBUG 5500 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:17.948 DEBUG 5500 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:17.949 DEBUG 5500 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:18.065 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:18.066 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:18.083 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:18.085 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:18.085 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:18.102 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:18.104 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:18.104 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:18.122 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:18.123 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:18.123 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:18.140 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:18.363 DEBUG 5500 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 9
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:18.366 DEBUG 5500 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?,?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:18.366 DEBUG 5500 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 174(Integer), 173(Integer), 172(Integer), 170(Integer), 169(Integer), 168(Integer), 167(Integer), 166(Integer), 163(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:18.385 DEBUG 5500 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:18.406 DEBUG 5500 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:18.407 DEBUG 5500 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:18.426 DEBUG 5500 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:26.037 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:26.037 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==> Parameters: 174(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:26.057 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:26.057 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:26.058 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==> Parameters: 174(Integer), %%(String), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:26.077 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:26.079 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:26.079 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==> Parameters: 174(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:26.098 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:32.902 DEBUG 5500 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:32.902 DEBUG 5500 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==> Parameters: 173(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:32.921 DEBUG 5500 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:32.922 DEBUG 5500 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:32.922 DEBUG 5500 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==> Parameters: 173(Integer), %%(String), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:32.942 DEBUG 5500 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:32.943 DEBUG 5500 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:32.943 DEBUG 5500 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==> Parameters: 173(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:32.964 DEBUG 5500 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:49.177 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:49.178 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==> Parameters: 174(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:49.198 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:49.199 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:49.199 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==> Parameters: 174(Integer), %%(String), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:49.219 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:49.220 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:49.220 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==> Parameters: 174(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:49.240 DEBUG 5500 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:51.496 DEBUG 5500 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:51.496 DEBUG 5500 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4793(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:51.515 DEBUG 5500 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:59.256 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:59.257 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==> Parameters: 173(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:59.276 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:59.280 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:59.281 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==> Parameters: 173(Integer), %%(String), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:59.301 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:59.305 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:59.306 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==> Parameters: 173(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:19:59.328 DEBUG 5500 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:01.629 DEBUG 5500 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:01.629 DEBUG 5500 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4792(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:01.649 DEBUG 5500 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:17.408 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM OS_PATENT_FIELD WHERE (NAME LIKE ? AND REPORT_TYPE LIKE ? AND REPORT_ID IS NULL)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:17.409 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==> Parameters: %%(String), %0%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:17.427 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:17.428 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (NAME LIKE ? AND REPORT_TYPE LIKE ? AND REPORT_ID IS NULL) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:17.428 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==> Parameters: %%(String), %0%(String), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:17.449 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:17.450 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM OS_PATENT_FIELD WHERE (NAME LIKE ? AND REPORT_TYPE LIKE ? AND REPORT_ID IS NULL) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:17.450 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==> Parameters: %%(String), %0%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:17.469 DEBUG 5500 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:19.743 DEBUG 5500 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:19.743 DEBUG 5500 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4774(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:19.763 DEBUG 5500 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:52.591 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.insert ==>  Preparing: INSERT INTO REPORT ( SIGN_PATENT_NO, NAME, TYPE, STATUS, PERSON_ID, PERSON_NAME, CLIENT_ID, CLIENT_NAME, DEPARTMENT_ID, DEPARTMENT_NAME, SCENARIO_ID, CREATE_PERSON_ID, CREATE_PERSON_NAME ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:52.592 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.insert ==> Parameters: JP2003093227A(String), JP2003093227A无效分析(String), 0(Integer), 1(Integer), 154(Integer), 朱豪(String), 27(Integer), 威世博(String), 58(Integer), syy(String), (String), 154(Integer), 朱豪(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:52.631 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:52.632 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_TYPE = ? AND REPORT_ID IS NULL)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:52.632 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:52.651 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:52.652 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD ( NAME, PTYPE, TYPE, STATUS, REMARK, CID, CREATE_TIME, REPORT_ID, REPORT_TYPE ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 17:20:52.652 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.insert ==> Parameters: 相关性(String), 1(Integer), 5(Integer), 1(Integer), (String), 114(Integer), 2022-12-12 10:19:53.0(Timestamp), 175(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:21:05.341 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:21:05.343 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4794(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:21:05.364 DEBUG 5500 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.442 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.463 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.498 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.503 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.504 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.526 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 10
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.535 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?,?,?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.537 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 176(Integer), 175(Integer), 174(Integer), 173(Integer), 172(Integer), 170(Integer), 169(Integer), 168(Integer), 167(Integer), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.554 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.570 DEBUG 14552 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.571 DEBUG 14552 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.598 DEBUG 14552 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.605 DEBUG 14552 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.606 DEBUG 14552 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.612 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.612 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.623 DEBUG 14552 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.624 DEBUG 14552 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.625 DEBUG 14552 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.629 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.642 DEBUG 14552 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.643 DEBUG 14552 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.644 DEBUG 14552 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:16.661 DEBUG 14552 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:35.497 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.insert ==>  Preparing: INSERT INTO REPORT ( SIGN_PATENT_NO, NAME, TYPE, STATUS, PERSON_ID, PERSON_NAME, CLIENT_ID, CLIENT_NAME, DEPARTMENT_ID, DEPARTMENT_NAME, SCENARIO_ID, CREATE_PERSON_ID, CREATE_PERSON_NAME ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:35.498 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.insert ==> Parameters: JP2003093227A(String), JP2003093227A无效分析(String), 0(Integer), 1(Integer), 154(Integer), 朱豪(String), 27(Integer), 威世博(String), 58(Integer), syy(String), (String), 154(Integer), 朱豪(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:35.530 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:35.540 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_TYPE = ? AND REPORT_ID IS NULL)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:35.540 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:35.558 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:35.563 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FIELD ( NAME, PTYPE, TYPE, STATUS, REMARK, CID, CREATE_TIME, REPORT_ID, REPORT_TYPE ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 17:25:35.566 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.insert ==> Parameters: 相关性(String), 1(Integer), 5(Integer), 1(Integer), (String), 114(Integer), 2022-12-12 10:19:53.0(Timestamp), 177(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:09.277 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:09.279 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4774(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:09.299 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.280 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectById ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.281 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectById ==> Parameters: 2892(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.297 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.298 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.updateById ==>  Preparing: UPDATE OS_PATENT_FILED_OPTION SET NAME=?, CID=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.299 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.updateById ==> Parameters: 相关(String), 4796(Integer), 2892(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.332 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectById ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.332 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectById ==> Parameters: 2893(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.349 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.350 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.updateById ==>  Preparing: UPDATE OS_PATENT_FILED_OPTION SET NAME=?, CID=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.351 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.updateById ==> Parameters: 不相关(String), 4796(Integer), 2893(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.783 DEBUG 14552 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.783 DEBUG 14552 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.800 DEBUG 14552 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.801 DEBUG 14552 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.801 DEBUG 14552 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.822 DEBUG 14552 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 10
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.823 DEBUG 14552 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?,?,?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.824 DEBUG 14552 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 177(Integer), 176(Integer), 175(Integer), 174(Integer), 173(Integer), 172(Integer), 170(Integer), 169(Integer), 168(Integer), 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.840 DEBUG 14552 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.862 DEBUG 14552 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.863 DEBUG 14552 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:26:30.880 DEBUG 14552 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.327 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.328 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.345 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.345 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.346 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.365 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 10
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.366 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?,?,?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.366 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 177(Integer), 176(Integer), 175(Integer), 174(Integer), 173(Integer), 172(Integer), 170(Integer), 169(Integer), 168(Integer), 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.383 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.404 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.404 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.421 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.598 DEBUG 14552 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.598 DEBUG 14552 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.615 DEBUG 14552 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.616 DEBUG 14552 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.616 DEBUG 14552 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.633 DEBUG 14552 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.635 DEBUG 14552 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.635 DEBUG 14552 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.652 DEBUG 14552 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.653 DEBUG 14552 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.653 DEBUG 14552 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:27:59.670 DEBUG 14552 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:04.365 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:04.365 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==> Parameters: 177(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:04.381 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:04.382 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:04.382 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==> Parameters: 177(Integer), %%(String), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:04.401 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:04.404 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:04.405 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==> Parameters: 177(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:04.421 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:06.227 DEBUG 14552 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:06.227 DEBUG 14552 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4796(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:06.244 DEBUG 14552 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:10.985 DEBUG 14552 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:10.985 DEBUG 14552 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==> Parameters: 175(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:11.002 DEBUG 14552 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:11.002 DEBUG 14552 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:11.003 DEBUG 14552 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==> Parameters: 175(Integer), %%(String), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:11.019 DEBUG 14552 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:11.020 DEBUG 14552 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:11.020 DEBUG 14552 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==> Parameters: 175(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:11.036 DEBUG 14552 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:13.142 DEBUG 14552 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:13.142 DEBUG 14552 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4794(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:13.159 DEBUG 14552 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.759 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.TaskMapper.delete ==>  Preparing: DELETE FROM TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.760 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.TaskMapper.delete ==> Parameters: 176(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.792 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.TaskMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.799 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.799 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 176(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.845 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 155
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.846 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.846 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 176(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.873 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.874 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.874 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 176(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.891 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.897 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTextMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_TEXT WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.898 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTextMapper.delete ==> Parameters: 176(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.930 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTextMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.935 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.936 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.delete ==> Parameters: 176(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.969 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.981 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTreeMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_TREE WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:24.981 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTreeMapper.delete ==> Parameters: 176(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:25.013 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldTreeMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:25.021 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:25.021 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: 176(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:25.054 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:25.059 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:25.059 DEBUG 14552 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldMapper.delete ==> Parameters: 176(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:28.207 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.TaskMapper.delete ==>  Preparing: DELETE FROM TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:28:28.208 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.TaskMapper.delete ==> Parameters: 176(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:01.219 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:01.220 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:01.240 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:01.240 DEBUG 14552 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:01.240 DEBUG 14552 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:01.259 DEBUG 14552 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:01.259 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:01.260 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:01.278 DEBUG 14552 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:01.601 DEBUG 14552 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:01.601 DEBUG 14552 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:01.619 DEBUG 14552 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.320 DEBUG 14552 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.320 DEBUG 14552 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.339 DEBUG 14552 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.346 DEBUG 14552 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.346 DEBUG 14552 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.363 DEBUG 14552 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.365 DEBUG 14552 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.365 DEBUG 14552 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.382 DEBUG 14552 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.389 DEBUG 14552 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.389 DEBUG 14552 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.405 DEBUG 14552 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.732 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.733 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.751 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.755 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.756 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.773 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.774 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.774 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.792 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.793 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.793 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:02.810 DEBUG 14552 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.308 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.TaskMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.309 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.309 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 176(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.354 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 155
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.355 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.355 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 176(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.381 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.382 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.382 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 176(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.399 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.400 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_TEXT WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.400 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.delete ==> Parameters: 176(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.434 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTextMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.435 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.435 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.delete ==> Parameters: 176(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.468 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldOptionMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.469 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_TREE WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.469 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.delete ==> Parameters: 176(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.502 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldTreeMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.505 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD_PATENT_LINK WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.506 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete ==> Parameters: 176(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.539 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldPatentLinkMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.540 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.delete ==>  Preparing: DELETE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:29:16.540 DEBUG 14552 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportFieldMapper.delete ==> Parameters: 176(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.490 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.508 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.540 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.542 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.543 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.560 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.560 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.562 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.581 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.886 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (PERSON_ID = ? AND TASK_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.886 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 154(Integer), 136(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.904 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.946 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.946 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.964 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.971 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.971 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 43(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.989 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.996 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:19.996 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14807(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:20.013 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:20.022 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:20.022 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: JP2003093227A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:20.039 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:21.044 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ? AND PATENT_NO = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:21.045 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 166(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:21.063 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:21.065 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:21.065 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 44(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:21.083 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:21.089 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:21.090 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 14812(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:21.110 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:21.111 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:21.112 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102727071A(String), 166(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 17:30:21.130 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:12.678 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:12.679 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:12.697 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:12.698 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:12.698 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 168(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:12.718 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:12.718 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:12.718 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:12.737 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:12.738 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:12.739 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 168(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:12.758 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:12.759 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:12.759 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:12.777 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:12.779 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:12.779 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:12.797 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:13.169 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:13.169 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 168(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:13.197 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 27
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:13.198 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:13.199 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 168(Integer), CN109924892B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:13.239 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 9
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.164 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.165 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.184 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.186 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.186 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.203 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.204 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.204 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.222 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.223 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.224 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.240 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.251 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.251 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 168(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.269 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.270 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.271 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 168(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.287 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.480 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.480 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 168(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.500 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 18
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.501 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.502 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 168(Integer), CN109924892B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:32.539 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.355 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.357 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.375 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.376 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.376 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.394 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.396 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.396 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.412 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.413 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.413 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.431 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.442 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.442 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 168(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.461 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.462 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.462 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 168(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.481 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.682 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.682 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 168(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.702 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 18
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.704 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.704 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 168(Integer), CN109924892B(String), 154(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:27:49.741 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.369 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.369 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.386 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.386 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.386 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.406 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.406 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.406 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.422 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.422 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.422 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.437 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.437 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.453 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.453 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.453 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.453 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.484 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 10
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.500 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?,?,?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.500 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 178(Integer), 177(Integer), 176(Integer), 175(Integer), 174(Integer), 173(Integer), 172(Integer), 170(Integer), 169(Integer), 168(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.515 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.562 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.562 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:38.578 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:42.942 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:42.942 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:42.958 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:42.958 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:42.959 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:42.960 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:42.960 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:42.976 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:42.977 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:42.977 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:42.977 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:42.978 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:42.978 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:42.995 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:42.996 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:42.996 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 10
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:42.996 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:42.997 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?,?,?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:42.997 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 178(Integer), 177(Integer), 176(Integer), 175(Integer), 174(Integer), 173(Integer), 172(Integer), 170(Integer), 169(Integer), 168(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:43.014 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:43.015 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:43.036 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:43.036 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:43.055 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:46.325 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:46.325 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:46.343 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:46.343 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:46.344 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:46.345 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:46.345 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:46.360 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:46.361 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:46.361 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:46.362 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:46.363 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:46.363 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:46.379 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:46.382 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:46.387 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:46.387 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:46.405 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:48.368 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:48.368 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:48.386 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:48.387 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:48.387 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:48.405 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:48.598 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:48.598 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:28:48.618 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 38
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.044 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.044 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.061 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.062 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.062 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.080 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.081 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.081 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.098 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.099 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.099 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.116 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.129 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.129 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.146 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.147 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.147 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.165 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.354 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.355 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.374 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 38
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.375 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.376 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 178(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:02.413 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.318 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.319 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.336 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.338 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.338 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.352 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.352 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 178(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.355 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.355 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.356 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.371 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.372 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.372 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.372 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.378 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.379 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.390 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.392 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0"
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.393 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.396 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.396 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.397 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.412 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.414 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.717 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.718 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:05.735 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:06.945 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:06.945 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: null, 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:06.963 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:06.964 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:06.964 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:06.981 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:06.982 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:06.982 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:07.000 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:07.000 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:07.000 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:07.017 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.740 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.740 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.756 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.756 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.756 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.756 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.756 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: null, 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.787 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.787 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.787 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.787 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.787 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.787 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.805 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.805 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.806 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.806 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.806 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.806 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.824 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.824 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.824 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.824 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.840 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.840 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.840 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.855 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.855 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.855 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:13.871 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:14.070 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:14.070 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:14.090 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 38
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:14.091 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:14.091 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 178(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:29:14.128 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:42.554 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:42.554 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: null, 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:42.571 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:42.574 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:42.575 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:42.593 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:42.596 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:42.597 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:42.615 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:42.616 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:42.617 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:42.635 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:44.069 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:44.069 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: null, 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:44.084 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:44.084 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:44.084 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:44.100 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:44.116 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:44.116 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:44.131 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:44.131 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:44.131 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:44.147 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:48.008 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:48.008 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: null, 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:48.039 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:48.039 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:48.039 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:48.055 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:48.055 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:48.055 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:48.070 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:48.070 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:48.070 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:48.086 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.288 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.288 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.307 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.310 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.311 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.317 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.318 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: null, 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.329 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.330 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.330 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.336 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.336 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.337 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.347 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.348 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.348 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.354 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.354 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.354 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.365 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.372 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.372 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.372 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.375 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.375 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.390 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.393 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.393 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.394 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.410 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.635 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.635 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.655 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 38
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.656 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.656 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 178(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:51.693 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.831 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.831 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.846 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.846 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.846 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.862 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.862 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 178(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.862 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.862 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.862 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.893 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.893 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.893 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.893 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.893 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.893 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.909 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.909 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0"
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.909 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.909 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.909 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.909 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.925 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:30:59.925 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:00.242 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:00.242 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:00.260 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:08.060 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:08.060 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: null, 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:08.078 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:08.079 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:08.079 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:08.096 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:08.097 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:08.098 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:08.116 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:08.116 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:08.116 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:08.134 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:21.292 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:21.292 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: null, 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:21.311 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:21.312 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:21.312 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:21.330 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:21.331 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:21.331 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:21.348 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:21.350 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:21.351 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:21.369 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:23.582 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:23.582 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: null, 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:23.600 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:23.601 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:23.601 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:23.618 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:23.619 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:23.619 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:23.637 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:23.639 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:23.639 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:23.658 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:29.345 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:29.346 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: null, 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:29.364 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:29.364 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:29.364 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:29.383 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:29.383 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:29.384 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:29.401 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:29.401 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:29.402 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:29.420 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.208 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.209 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.229 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.232 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.232 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.232 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.232 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: null, 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.250 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.251 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.254 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.254 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.254 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.254 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.271 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.272 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.275 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.276 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.276 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.276 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.294 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.295 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.295 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.296 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.302 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.303 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.313 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.322 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.323 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.323 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.341 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.532 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.532 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.555 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 38
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.557 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.558 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 178(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:32.596 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.095 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.096 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.115 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.116 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.116 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.130 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.130 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 178(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.134 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.135 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.135 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.149 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.152 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.153 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.153 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.155 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.156 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.171 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.172 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0"
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.173 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.174 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.175 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.176 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.191 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.195 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.531 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.531 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:35.548 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.071 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.071 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.087 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.087 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.087 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.087 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.087 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.106 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.106 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.106 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.106 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.106 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.106 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.122 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.122 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.122 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.122 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.122 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.122 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.138 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.138 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.138 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 178(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.138 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.138 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.138 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.153 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.153 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.153 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.153 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.153 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.153 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.169 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.169 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.169 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.184 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.184 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.184 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.200 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.200 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0"
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.200 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.200 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.216 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.446 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.446 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.462 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 38
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.462 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.462 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 178(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.493 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.686 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.686 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:38.702 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:39.987 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:39.988 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: null, 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:40.008 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:40.010 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:40.011 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:40.030 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:40.033 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:40.033 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:40.052 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:40.053 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:40.054 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:31:40.072 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:45.085 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:45.085 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: null, 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:45.104 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:45.106 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:45.107 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:45.126 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:45.126 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:45.127 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:45.145 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:45.145 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:45.145 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:45.164 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:49.887 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:49.887 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 178(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:49.908 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:49.910 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:49.910 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:49.925 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:49.925 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:49.925 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:49.941 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:49.941 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:49.941 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:32:49.972 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.305 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.305 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.322 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.337 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.337 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.353 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.353 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.353 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.384 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 10
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.384 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?,?,?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.384 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 179(Integer), 178(Integer), 177(Integer), 176(Integer), 175(Integer), 174(Integer), 173(Integer), 172(Integer), 170(Integer), 169(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.400 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.416 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.416 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.447 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.478 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.478 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.494 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.494 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.494 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.525 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.525 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.525 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:53.541 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:55.971 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:55.971 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==> Parameters: 179(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:55.991 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:55.993 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:55.994 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==> Parameters: 179(Integer), %%(String), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:56.015 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:56.018 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM OS_PATENT_FIELD WHERE (REPORT_ID = ? AND NAME LIKE ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:56.019 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==> Parameters: 179(Integer), %%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:56.038 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:57.668 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:57.668 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4798(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:48:57.684 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:04.971 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM OS_PATENT_FIELD WHERE (NAME LIKE ? AND REPORT_TYPE LIKE ? AND REPORT_ID IS NULL)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:04.971 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount ==> Parameters: %%(String), %0%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:04.987 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:04.987 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (NAME LIKE ? AND REPORT_TYPE LIKE ? AND REPORT_ID IS NULL) ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:04.987 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectPage ==> Parameters: %%(String), %0%(String), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:05.015 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectPage <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:05.015 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM OS_PATENT_FIELD WHERE (NAME LIKE ? AND REPORT_TYPE LIKE ? AND REPORT_ID IS NULL) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:05.016 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectCount ==> Parameters: %%(String), %0%(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:05.035 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportFieldMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:07.702 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:07.702 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4774(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:07.734 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:13.508 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ? AND NAME = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:13.509 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4774(Integer), 相关(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:13.530 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:13.544 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FILED_OPTION ( NAME, CID ) VALUES ( ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:13.545 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.insert ==> Parameters: 相关(String), 4774(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:13.585 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportFieldOptionMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:21.951 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ? AND NAME = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:21.952 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4774(Integer), 不相关(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:21.971 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:21.973 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FILED_OPTION ( NAME, CID ) VALUES ( ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:21.973 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.insert ==> Parameters: 不相关(String), 4774(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:22.000 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportFieldOptionMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:27.975 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:27.975 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4798(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:27.994 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:33.693 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ? AND NAME = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:33.693 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4798(Integer), 相关(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:33.713 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:33.713 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FILED_OPTION ( NAME, CID ) VALUES ( ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:33.713 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.insert ==> Parameters: 相关(String), 4798(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:33.756 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportFieldOptionMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:39.384 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==>  Preparing: SELECT ID,NAME,CID AS fieldId FROM OS_PATENT_FILED_OPTION WHERE (CID = ? AND NAME = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:39.385 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList ==> Parameters: 4798(Integer), 不相关(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:39.404 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:39.406 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.insert ==>  Preparing: INSERT INTO OS_PATENT_FILED_OPTION ( NAME, CID ) VALUES ( ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:39.406 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.insert ==> Parameters: 不相关(String), 4798(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 18:49:39.447 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportFieldOptionMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:02.441 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:02.442 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 179(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:02.460 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:02.463 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:02.463 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 179(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:02.480 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:03.642 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:03.642 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:03.662 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:03.662 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:03.663 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 179(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:03.683 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:03.684 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:03.684 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:03.702 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:03.702 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:03.702 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 179(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:03.720 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:03.720 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:03.720 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:03.738 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:03.741 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:03.742 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:03.760 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:04.962 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:04.962 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 179(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 19:02:04.981 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.112 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.112 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.130 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.131 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.131 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.152 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 10
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.153 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?,?,?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.153 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 201(Integer), 200(Integer), 199(Integer), 198(Integer), 197(Integer), 196(Integer), 195(Integer), 194(Integer), 193(Integer), 192(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.176 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.213 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.214 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.232 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.269 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.269 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.288 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.288 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.289 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.307 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.308 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.308 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.327 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.328 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.328 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:17.348 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.481 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.481 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.501 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.502 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.502 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.521 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.521 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.522 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.540 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.540 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.541 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.560 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.566 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.567 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.586 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.586 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.587 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.606 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.793 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.794 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.837 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 66
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.838 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.838 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.876 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.878 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.879 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 1.一种框式电饭煲(String), 1.一种框式电饭煲(String), 741106(Integer), 114(Integer), 0(Integer), 201(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.879 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 包括锅体、框体(String), 包括锅体、框体(String), 741106(Integer), 114(Integer), 0(Integer), 201(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.880 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 其特征在于(String), 其特征在于(String), 741106(Integer), 114(Integer), 0(Integer), 201(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.880 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 741106(Integer), 114(Integer), 0(Integer), 201(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:21.880 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 顶部与承载部形成开放的锅体取放空间(String), 顶部与承载部形成开放的锅体取放空间(String), 741106(Integer), 114(Integer), 0(Integer), 201(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.002 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.002 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 741107(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要2(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.042 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.042 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.043 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 741108(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.081 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.081 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.082 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 741109(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.122 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.122 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.123 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 741110(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.161 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.163 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.164 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 741111(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.204 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.204 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.205 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 741112(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.244 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.244 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.245 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 741113(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.284 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.284 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.285 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 741114(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.324 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.324 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.324 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 741115(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要10(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:22.364 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:26.393 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:26.393 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:26.424 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 14
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:26.424 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, EXPLAIN_TEXT, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:26.424 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 包括锅体、框体(String), 1.一种框式电饭煲,包括锅体、框体(String), 741106(Integer), 114(Integer), 0(Integer), 201(Integer), 1.一种框式电饭煲,包括锅体、框体(String), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:26.424 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 其特征在于(String), 其特征在于(String), 741106(Integer), 114(Integer), 0(Integer), 201(Integer), 其特征在于(String), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:26.424 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 741106(Integer), 114(Integer), 0(Integer), 201(Integer), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:26.424 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 顶部与承载部形成开放的锅体取放空间(String), 顶部与承载部形成开放的锅体取放空间(String), 741106(Integer), 114(Integer), 0(Integer), 201(Integer), 顶部与承载部形成开放的锅体取放空间(String), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:26.424 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, EXPLAIN_TEXT, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:26.424 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 741107(Integer), 114(Integer), 0(Integer), 201(Integer), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), -1(Integer), 权要2(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:26.424 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 741108(Integer), 114(Integer), 0(Integer), 201(Integer), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:26.424 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 741109(Integer), 114(Integer), 0(Integer), 201(Integer), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:26.424 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 741110(Integer), 114(Integer), 0(Integer), 201(Integer), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:26.440 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 741111(Integer), 114(Integer), 0(Integer), 201(Integer), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:26.440 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 741112(Integer), 114(Integer), 0(Integer), 201(Integer), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:26.440 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 741113(Integer), 114(Integer), 0(Integer), 201(Integer), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:26.440 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 741114(Integer), 114(Integer), 0(Integer), 201(Integer), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:26.440 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 741115(Integer), 114(Integer), 0(Integer), 201(Integer), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), -1(Integer), 权要10(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.094 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.094 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.109 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.109 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.109 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.125 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.125 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 201(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.125 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.125 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.125 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.141 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.141 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.141 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.141 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.141 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.141 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.156 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.156 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.156 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.156 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.172 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.172 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.172 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.187 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.637 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.637 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:28.669 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:29.773 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:29.774 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:29.795 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:29.797 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:29.798 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:29.819 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:30.009 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:30.009 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:30.040 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 79
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:30.040 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:30.040 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:30.071 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 9
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:47.995 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:47.996 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.000 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.016 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.016 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.031 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.031 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 201(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.031 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.031 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.031 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.047 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.047 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.047 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.047 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.047 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.047 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.063 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.063 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.063 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.063 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.063 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.078 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.078 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.094 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.554 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.554 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:48.570 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:59.780 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:59.780 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:59.800 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:59.802 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:59.803 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:59.822 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:59.823 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:59.823 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:59.842 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:59.844 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:59.845 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:59.864 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:59.865 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:59.866 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:09:59.885 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:00.344 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:00.345 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:00.364 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:02.549 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:02.550 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:02.569 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:02.570 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:02.570 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:02.589 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:02.591 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:02.592 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:02.611 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:02.614 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:02.614 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:02.634 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:02.635 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:02.636 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:02.656 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:03.131 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:03.131 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:03.151 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:05.534 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:05.534 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:05.554 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.157 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.157 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.177 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.178 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.178 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.197 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.311 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.insert ==>  Preparing: INSERT INTO COMPARE_FILES ( REPORT_ID, PATENT_NO ) VALUES ( ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.312 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.insert ==> Parameters: 201(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.312 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.insert ==> Parameters: 201(Integer), JP1994296558A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.313 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.insert ==> Parameters: 201(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.314 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.insert ==> Parameters: 201(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.464 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.465 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.484 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.484 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.485 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.503 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.504 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.504 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.523 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.524 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.524 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.543 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.543 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.543 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.563 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.973 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.973 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:06.992 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.100 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.100 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.100 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.100 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.118 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.118 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.119 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.120 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.120 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.121 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.136 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.137 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.137 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.140 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.140 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.140 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.155 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.155 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.155 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.159 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.159 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.161 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.172 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.173 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.173 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 201(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.179 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.179 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.179 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.190 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.190 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.191 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.198 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.198 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.199 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.211 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.212 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.212 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.218 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.218 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.218 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.230 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.236 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.442 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.442 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.464 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 70
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.465 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.465 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.503 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.503 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.503 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 741107(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要2(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.543 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.543 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.543 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 741108(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.577 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.577 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.582 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.583 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.583 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 741109(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.594 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.623 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.623 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.623 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 741110(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.662 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.662 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.662 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 741111(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.702 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.703 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.704 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 741112(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.745 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.746 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.747 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 741113(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.787 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.787 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.787 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 741114(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.826 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.826 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.826 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 741115(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要10(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:20.866 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.329 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.329 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.348 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.348 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.348 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.366 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.366 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.366 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.366 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.366 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.384 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.384 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.384 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.385 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.385 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.385 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.402 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.405 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.405 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.405 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.416 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.417 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.424 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.425 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.425 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.434 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.434 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.435 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.443 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.443 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 201(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.444 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.444 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.444 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.452 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.461 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.461 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.462 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.463 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.479 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.479 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.479 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.498 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.640 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.640 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.679 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 79
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.680 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.681 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.718 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 9
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.878 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.878 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:29.895 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:37.618 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:37.618 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:37.636 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:37.637 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?,?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:37.637 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:37.657 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 10
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:37.659 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?,?,?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:37.660 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 191(Integer), 190(Integer), 189(Integer), 188(Integer), 187(Integer), 186(Integer), 185(Integer), 184(Integer), 179(Integer), 178(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:37.678 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:37.703 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:37.703 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:37.721 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:39.412 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:39.412 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:39.431 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:39.431 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?,?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:39.431 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 20(Long), 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:39.449 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 10
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:39.450 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?,?,?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:39.450 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 177(Integer), 176(Integer), 175(Integer), 174(Integer), 173(Integer), 172(Integer), 170(Integer), 169(Integer), 168(Integer), 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:39.468 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:39.488 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:39.488 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:39.506 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:45.455 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:45.456 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:45.472 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:45.472 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:45.474 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:45.475 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:45.475 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:45.491 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:45.493 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:45.493 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:45.495 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:45.497 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:45.497 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:45.512 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:45.518 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:45.519 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:45.520 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:45.538 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:46.404 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:46.404 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:46.408 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:46.408 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:46.408 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:46.440 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:46.638 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:46.638 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:46.669 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:48.629 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:48.630 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:48.649 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:48.651 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:48.651 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:48.670 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.647 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==>  Preparing: SELECT ID,NAME,PTYPE,TYPE,STATUS,REMARK,CID AS createBy,CREATE_TIME,REPORT_ID,REPORT_TYPE FROM OS_PATENT_FIELD WHERE (REPORT_ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.647 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.647 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.647 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 167(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.662 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.662 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.662 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.662 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportFieldMapper.selectList <==      Total: 2
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.678 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.694 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.694 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.694 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.694 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.709 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.709 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.709 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.725 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 16
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.725 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.725 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.725 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:49.741 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.364 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.364 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.383 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.383 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.384 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.403 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.597 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.598 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.617 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.631 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==>  Preparing: SELECT ID,PATENT_NO,POSITION,FIELDS,CONTENT,PERSON_ID,PARESING_PROCESS,FILE_PATH,REPORT_ID,TASK_ID FROM COMPARE_RECORDS WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.632 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.651 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareRecordsMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.651 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==>  Preparing: SELECT ID,RECORDS_ID,FEATURE_ID,COM_RESULT FROM ASSO_RECORDS_FEATURES WHERE (RECORDS_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.651 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList ==> Parameters: 52(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.670 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoRecordsFeatureMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.671 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.671 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 24185(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.690 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.693 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (PATENT_NO IN (?) AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.693 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: CN102522896B(String), 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.712 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.937 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareScenariosMapper.selectList ==>  Preparing: SELECT ID,RIGHT_ID,RIGHTNAME,REPORT_ID,SIGN_PATENT_NO,CONTRAST AS contrastResult,PERSON_ID FROM COMPARE_SCENARIOS WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.937 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareScenariosMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:50.956 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareScenariosMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:51.446 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:51.446 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:51.467 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:51.469 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:51.470 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:51.490 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:51.679 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:51.680 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN102522896B(String), 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:51.699 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:51.804 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?) ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:51.804 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:51.823 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:51.823 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?))
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:51.824 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 167(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:10:51.843 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.465 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.465 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.479 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.479 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.482 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.482 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.483 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.499 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.499 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.499 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.501 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.502 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.502 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.519 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 10
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.519 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.519 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?,?,?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.519 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 201(Integer), 200(Integer), 199(Integer), 198(Integer), 197(Integer), 196(Integer), 195(Integer), 194(Integer), 193(Integer), 192(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.519 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.520 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.537 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.538 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.558 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.558 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:01.578 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.378 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.378 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.394 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.394 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.409 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.409 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.409 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.409 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.409 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.409 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.425 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.425 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.425 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.425 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.425 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.425 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.440 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.440 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.440 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.456 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.456 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.456 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.456 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.456 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 201(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.456 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.456 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.456 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.472 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.472 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.472 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.472 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.472 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.472 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.472 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.487 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.487 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.487 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.487 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.487 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.487 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.508 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.508 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.701 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.701 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.722 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 70
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.722 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.722 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.753 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.753 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.753 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 741107(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要2(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.800 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.800 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.800 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 741108(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.831 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.831 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.831 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 741109(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.878 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.878 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.878 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 741110(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.878 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.878 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.894 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.925 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.925 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.925 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 741111(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.956 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.956 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:11.956 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 741112(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:12.005 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:12.006 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:12.006 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 741113(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:12.045 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:12.045 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:12.045 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 741114(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:12.084 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:12.086 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:12.087 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 741115(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要10(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:12.126 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:15.209 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:15.209 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:15.225 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:15.225 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:15.225 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:15.240 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:15.240 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:15.240 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:15.256 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:15.256 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:15.256 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:15.287 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:15.287 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:15.287 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:15.308 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:15.699 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:15.699 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:15.715 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:16.147 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:16.147 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:16.166 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:16.738 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:16.738 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:16.757 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:16.757 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:16.757 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:16.777 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:16.874 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.insert ==>  Preparing: INSERT INTO COMPARE_FILES ( REPORT_ID, PATENT_NO ) VALUES ( ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:16.875 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.insert ==> Parameters: 201(Integer), CN201312722Y(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:16.971 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:16.972 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:16.991 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 5
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:16.991 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:16.992 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:17.010 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:17.010 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:17.011 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:17.030 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:17.030 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:17.030 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:17.049 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:17.049 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:17.049 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:17.070 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:17.434 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:17.434 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:17.453 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:20.991 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:20.992 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:21.011 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 5
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:21.011 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:21.011 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:21.030 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:21.030 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:21.031 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:21.050 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:21.052 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:21.053 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:21.073 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:21.074 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:21.075 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:21.095 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:21.441 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:21.442 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:21.460 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:23.333 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:23.333 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:23.353 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:23.928 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:23.929 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:23.948 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 5
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:23.950 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:23.951 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:23.970 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:24.112 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:24.112 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:24.131 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 5
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:24.133 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:24.134 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:24.153 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:24.154 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:24.154 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:24.173 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:24.176 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:24.176 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:24.196 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:24.197 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:24.197 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:24.217 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:24.576 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:24.576 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:24.595 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.460 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.461 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.462 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.462 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.479 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 5
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.480 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.480 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.481 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.481 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.482 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.497 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.497 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.497 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.501 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.501 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.501 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.515 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.517 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.518 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.520 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.522 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.523 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.530 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.532 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 201(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.535 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.536 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.536 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.542 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.551 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.551 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.551 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.553 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.553 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.554 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.570 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.570 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.571 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.571 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.571 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.571 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.590 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.591 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.786 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.786 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.808 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 79
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.809 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.809 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.850 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 9
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.939 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.939 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:26.958 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:29.346 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:29.346 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:29.362 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 5
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:29.362 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:29.362 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:29.378 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:29.378 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:29.378 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:29.393 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:29.393 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:29.393 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:29.425 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:29.425 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:29.425 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:29.440 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:29.837 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:29.837 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:29.852 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.114 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.114 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.135 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.720 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.721 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.740 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 5
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.742 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.742 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.762 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.917 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.917 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.936 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 5
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.936 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.936 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.955 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.955 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.956 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.975 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.975 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.976 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.994 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.994 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:30.995 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:31.013 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:31.387 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:31.388 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:31.407 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:36.277 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:36.278 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 201(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:36.296 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:36.297 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:36.297 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:36.317 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 5
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:36.317 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:36.317 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:36.336 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:36.336 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:36.336 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:36.356 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:57.796 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:57.797 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 201(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:57.816 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:57.818 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:57.819 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:57.838 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:57.838 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:57.838 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:57.857 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:57.858 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:57.859 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:11:57.879 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.892 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.892 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.911 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.911 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.911 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.926 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.927 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 201(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.931 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.932 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.932 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.944 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.944 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.944 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.950 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.952 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.953 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.964 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.965 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.965 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.972 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.973 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.973 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.983 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:10.993 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:11.444 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:11.445 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:11.463 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.332 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.332 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.333 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.333 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.350 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.351 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.351 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.352 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.352 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.352 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.368 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.368 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.368 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.372 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.372 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.372 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.386 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.386 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.386 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.391 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.392 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.392 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.398 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.398 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 201(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.404 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.404 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.404 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.411 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.416 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.416 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.416 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.416 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.416 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.422 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.434 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.434 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.434 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.435 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.435 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.435 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.452 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.458 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.637 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.637 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.659 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 70
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.660 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.661 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.698 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.698 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.698 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 741107(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要2(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.738 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.738 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.738 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 741108(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.778 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.778 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.778 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 741109(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.818 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.818 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.818 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 741110(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.840 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.840 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.856 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.857 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.857 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.857 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 741111(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.897 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.897 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.897 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 741112(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.936 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.937 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.938 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 741113(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.977 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.978 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:13.979 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 741114(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:14.019 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:14.020 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:14.020 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 741115(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要10(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:14.059 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:17.809 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:17.810 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:17.830 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:17.832 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:17.833 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:17.852 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:17.854 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:17.854 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:17.873 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:17.875 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:17.876 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:17.895 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:17.896 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:17.896 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:17.917 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:18.368 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:18.368 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:18.384 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:18.725 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:18.725 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:18.740 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.329 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.329 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.349 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.351 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.351 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.370 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.472 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.insert ==>  Preparing: INSERT INTO COMPARE_FILES ( REPORT_ID, PATENT_NO ) VALUES ( ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.473 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.insert ==> Parameters: 201(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.473 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.insert ==> Parameters: 201(Integer), JP1994296558A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.473 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.insert ==> Parameters: 201(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.473 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.insert ==> Parameters: 201(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.473 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.insert ==> Parameters: 201(Integer), CN2258371Y(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.473 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.insert ==> Parameters: 201(Integer), KR1020160016352A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.664 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.665 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.684 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.686 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.687 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.706 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.708 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.708 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.727 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.729 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.730 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.749 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.750 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.751 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:19.771 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:20.100 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:20.100 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:20.115 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.261 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.261 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.262 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.263 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.280 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.280 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.280 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.283 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.284 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.284 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.300 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.300 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.300 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.301 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.301 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.301 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.318 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.318 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.319 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.319 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.319 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.319 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.329 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.329 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 201(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.336 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.337 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.337 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.339 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.346 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.346 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.347 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.347 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.347 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.356 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.365 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.365 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.365 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.365 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.366 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.366 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.383 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.385 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.576 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.576 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.601 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 79
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.604 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.604 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.645 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 9
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.699 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.699 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:24.718 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:27.338 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:27.339 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 201(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:27.359 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:27.361 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:27.362 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:27.380 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:27.383 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:27.383 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:27.402 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:27.403 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:27.403 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:27.423 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:44.806 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:44.807 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 201(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:44.823 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:44.823 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:44.823 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:44.838 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:44.838 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:44.838 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:44.854 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:44.854 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:44.854 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:44.885 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:59.660 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:59.660 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:59.679 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:59.682 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.updateById ==>  Preparing: UPDATE REPORT SET SIGN_PATENT_NO=?, NAME=?, PRO_TEC=?, TYPE=?, STATUS=?, CREATE_TIME=?, PERSON_ID=?, PERSON_NAME=?, CLIENT_ID=?, CLIENT_NAME=?, DEPARTMENT_ID=?, DEPARTMENT_NAME=?, SCENARIO_ID=?, PROJECT_ID=?, SPLIT_BY=?, SPLIT_TYPE=?, CREATE_PERSON_ID=?, CREATE_PERSON_NAME=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:59.684 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.updateById ==> Parameters: CN109924892B(String), CN109924892B无效分析(String), (String), 0(Integer), 2(Integer), 2022-12-12 20:05:56.0(Timestamp), 4(Integer), 瀚海管理员(String), 61(Integer), 陈宇(String), 49(Integer), 安徽省瀚海新材料股份有限公司(String), 1(String), 179(Integer), 2(Integer), 0(Integer), 103(Integer), 沈永艺(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:59.721 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:59.844 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT PATENT_NO FROM COMPARE_FILES WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:59.844 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:59.864 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:59.865 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:59.865 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:59.884 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:59.884 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:59.884 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 20:12:59.903 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:05.639 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:05.639 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:05.655 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:05.655 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.updateById ==>  Preparing: UPDATE REPORT SET SIGN_PATENT_NO=?, NAME=?, PRO_TEC=?, TYPE=?, STATUS=?, CREATE_TIME=?, PERSON_ID=?, PERSON_NAME=?, CLIENT_ID=?, CLIENT_NAME=?, DEPARTMENT_ID=?, DEPARTMENT_NAME=?, SCENARIO_ID=?, PROJECT_ID=?, SPLIT_BY=?, SPLIT_TYPE=?, CREATE_PERSON_ID=?, CREATE_PERSON_NAME=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:05.655 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.updateById ==> Parameters: CN109924892B(String), CN109924892B无效分析(String), (String), 0(Integer), 2(Integer), 2022-12-12 20:05:56.0(Timestamp), 4(Integer), 瀚海管理员(String), 61(Integer), 陈宇(String), 49(Integer), 安徽省瀚海新材料股份有限公司(String), 1(String), 179(Integer), 2(Integer), 0(Integer), 103(Integer), 沈永艺(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:05.686 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:05.805 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT PATENT_NO FROM COMPARE_FILES WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:05.805 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:05.823 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:05.823 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:05.823 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:05.838 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:05.838 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:05.838 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:05.854 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:14.918 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:14.918 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:14.937 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:14.937 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.updateById ==>  Preparing: UPDATE REPORT SET SIGN_PATENT_NO=?, NAME=?, PRO_TEC=?, TYPE=?, STATUS=?, CREATE_TIME=?, PERSON_ID=?, PERSON_NAME=?, CLIENT_ID=?, CLIENT_NAME=?, DEPARTMENT_ID=?, DEPARTMENT_NAME=?, SCENARIO_ID=?, PROJECT_ID=?, SPLIT_BY=?, SPLIT_TYPE=?, CREATE_PERSON_ID=?, CREATE_PERSON_NAME=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:14.937 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.updateById ==> Parameters: CN109924892B(String), CN109924892B无效分析(String), (String), 0(Integer), 2(Integer), 2022-12-12 20:05:56.0(Timestamp), 4(Integer), 瀚海管理员(String), 61(Integer), 陈宇(String), 49(Integer), 安徽省瀚海新材料股份有限公司(String), 1(String), 179(Integer), 2(Integer), 0(Integer), 103(Integer), 沈永艺(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:14.968 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:15.093 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT PATENT_NO FROM COMPARE_FILES WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:15.093 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:15.112 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:15.112 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:15.112 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:15.132 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:15.132 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:15.132 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: null
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:15.152 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:45.202 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:45.203 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 201(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:45.222 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:45.222 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:45.222 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:45.242 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:45.242 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:45.242 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:45.261 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:45.261 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:45.261 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:45.281 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:49.929 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:49.930 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:49.950 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:49.950 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:49.950 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:49.963 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:49.963 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 201(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:49.970 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:49.970 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:49.970 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:49.980 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:49.980 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:49.980 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:49.990 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:49.990 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:49.990 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:49.998 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:49.998 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:49.998 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.000 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.016 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.016 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.016 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.016 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.016 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.033 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.035 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.035 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.036 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.055 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.278 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.279 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.304 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 70
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.306 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.306 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.344 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.344 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.344 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 741107(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要2(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.384 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.384 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.384 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 741108(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.424 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.425 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.426 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 741109(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.465 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.466 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.467 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 741110(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.506 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.507 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.507 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 741111(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.547 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.547 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.547 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 741112(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.586 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.587 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.587 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 741113(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.627 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.627 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.627 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 741114(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.666 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.666 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.667 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 741115(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要10(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:13:50.706 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:14.412 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:14.412 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 201(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:14.431 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:14.433 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:14.433 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:14.452 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:14.452 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:14.452 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:14.472 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:14.472 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:14.472 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:14.491 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:27.445 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:27.445 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:27.465 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:27.465 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.updateById ==>  Preparing: UPDATE REPORT SET SIGN_PATENT_NO=?, NAME=?, PRO_TEC=?, TYPE=?, STATUS=?, CREATE_TIME=?, PERSON_ID=?, PERSON_NAME=?, CLIENT_ID=?, CLIENT_NAME=?, DEPARTMENT_ID=?, DEPARTMENT_NAME=?, SCENARIO_ID=?, PROJECT_ID=?, SPLIT_BY=?, SPLIT_TYPE=?, CREATE_PERSON_ID=?, CREATE_PERSON_NAME=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:27.465 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.updateById ==> Parameters: CN109924892B(String), CN109924892B无效分析(String), (String), 0(Integer), 2(Integer), 2022-12-12 20:05:56.0(Timestamp), 4(Integer), 瀚海管理员(String), 61(Integer), 陈宇(String), 49(Integer), 安徽省瀚海新材料股份有限公司(String), 1(String), 179(Integer), 2(Integer), 0(Integer), 103(Integer), 沈永艺(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:27.503 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:27.614 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT PATENT_NO FROM COMPARE_FILES WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:27.615 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:27.635 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.891 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.892 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.893 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.893 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.911 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.911 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.911 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.911 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.912 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.912 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.929 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.929 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.929 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.931 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 10
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.932 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?,?,?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.932 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 202(Integer), 201(Integer), 200(Integer), 199(Integer), 198(Integer), 197(Integer), 196(Integer), 195(Integer), 194(Integer), 193(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.947 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.949 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.950 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.950 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.968 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.983 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:50.983 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.002 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.246 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.246 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.262 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.262 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.262 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.277 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.277 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.277 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.293 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.293 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.293 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.308 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.308 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.308 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.308 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.308 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.324 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.324 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.324 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 201(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.324 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.340 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.340 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.340 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.355 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.371 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.371 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.387 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.387 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.387 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.407 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.516 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.516 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.553 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 79
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.553 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.553 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:51.600 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 9
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.427 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.427 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 201(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.445 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.447 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.448 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.466 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.468 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.469 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.479 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.479 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 201(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.486 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.486 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.487 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.497 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.498 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.498 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.505 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.516 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.516 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.516 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.534 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.534 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.534 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:52.551 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:53.609 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:53.609 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 201(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:53.626 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:53.626 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:53.626 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:53.644 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:53.645 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:53.645 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:53.662 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:53.662 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:53.662 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:14:53.680 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.916 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.916 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.933 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.934 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.934 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.937 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.937 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.952 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.952 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.952 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.955 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.955 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.955 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.970 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.970 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.970 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.973 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 10
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.974 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?,?,?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.974 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 202(Integer), 201(Integer), 200(Integer), 199(Integer), 198(Integer), 197(Integer), 196(Integer), 195(Integer), 194(Integer), 193(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.987 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:03.992 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:04.008 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:04.008 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:04.024 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:05.970 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:05.970 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:05.988 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:05.989 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:05.989 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:05.996 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:05.996 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 201(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.000 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.000 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.000 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.000 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.000 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.000 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.016 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.016 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.016 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.016 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.016 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.016 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.037 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.037 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.037 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.037 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.053 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.053 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.053 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.068 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.068 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.068 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.084 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.271 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.271 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.306 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 70
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.306 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.306 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.339 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.339 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.339 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 741107(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要2(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.370 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.370 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.370 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 741108(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.407 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.407 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.407 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 741109(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.438 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.438 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.438 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 741110(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.485 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.485 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.485 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 741111(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.522 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.522 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.522 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 741112(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.553 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.553 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.553 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 741113(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.584 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.584 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.584 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 741114(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.631 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.631 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.631 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 741115(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要10(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:06.662 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.815 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.815 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.830 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.830 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 201(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.834 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.834 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.834 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.848 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.848 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.848 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.852 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.852 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.852 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.865 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.865 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.865 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.869 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.869 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.869 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.883 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.883 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.883 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.887 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.902 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.904 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.904 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.922 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.922 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.922 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:39.940 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:40.127 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:40.127 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:40.147 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 79
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:40.148 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:40.148 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:40.185 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 9
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.186 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.186 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.204 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.207 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.207 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.223 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.224 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 201(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.224 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.227 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.227 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.244 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.245 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.246 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.247 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.247 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.248 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.265 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.265 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.265 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.266 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.266 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.266 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.285 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.288 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.624 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.624 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.642 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.818 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.819 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.835 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.836 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.836 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:45.855 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.048 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.048 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.069 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 70
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.069 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.069 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.103 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.105 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.105 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 741107(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要2(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.141 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.141 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.141 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 741108(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.177 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.178 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.179 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 741109(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.215 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.215 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.215 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 741110(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.251 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.251 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.251 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 741111(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.287 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.288 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.288 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 741112(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.326 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.326 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.326 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 741113(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.363 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.364 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.365 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 741114(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.401 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.401 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.401 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 741115(Integer), 114(Integer), 0(Integer), 201(Integer), -1(Integer), 权要10(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:46.438 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:50.443 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:50.444 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:50.479 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:50.480 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, EXPLAIN_TEXT, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:50.481 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 其特征在于(String), 1.一种框式电饭煲,包括锅体、框体,其特征在于(String), 741106(Integer), 114(Integer), 0(Integer), 201(Integer), 1.一种框式电饭煲,包括锅体、框体,其特征在于(String), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:50.481 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 741106(Integer), 114(Integer), 0(Integer), 201(Integer), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:50.481 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 顶部与承载部形成开放的锅体取放空间(String), 顶部与承载部形成开放的锅体取放空间(String), 741106(Integer), 114(Integer), 0(Integer), 201(Integer), 顶部与承载部形成开放的锅体取放空间(String), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:50.481 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, EXPLAIN_TEXT, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:50.481 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 741107(Integer), 114(Integer), 0(Integer), 201(Integer), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), -1(Integer), 权要2(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:50.482 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 741108(Integer), 114(Integer), 0(Integer), 201(Integer), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:50.482 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 741109(Integer), 114(Integer), 0(Integer), 201(Integer), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:50.482 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 741110(Integer), 114(Integer), 0(Integer), 201(Integer), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:50.482 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 741111(Integer), 114(Integer), 0(Integer), 201(Integer), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:50.482 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 741112(Integer), 114(Integer), 0(Integer), 201(Integer), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:50.483 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 741113(Integer), 114(Integer), 0(Integer), 201(Integer), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:50.483 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 741114(Integer), 114(Integer), 0(Integer), 201(Integer), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:50.483 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 741115(Integer), 114(Integer), 0(Integer), 201(Integer), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), -1(Integer), 权要10(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.909 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.909 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.924 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.924 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.924 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.940 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.940 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.940 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 201(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.940 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.940 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.971 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.971 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 12
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.971 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.971 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.971 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.971 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.987 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.987 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.987 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.987 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.987 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:51.987 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体,其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:52.013 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:52.015 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:52.339 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:52.339 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:52.357 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:52.947 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:52.947 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:52.965 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:52.965 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:52.965 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:52.983 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:53.169 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:53.169 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:53.196 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 78
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:53.197 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:53.197 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:15:53.234 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 9
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:02.431 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:02.431 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:02.466 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 3
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:02.466 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, EXPLAIN_TEXT, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:02.466 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 其特征在于(String), 1.一种框式电饭煲,包括锅体、框体,(String), 741106(Integer), 114(Integer), 0(Integer), 201(Integer), 1.一种框式电饭煲,包括锅体、框体,其特征在于(String), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:02.467 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, EXPLAIN_TEXT, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:02.467 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), (String), 其特征在于(String), 741106(Integer), 114(Integer), 0(Integer), 201(Integer), (String), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:02.467 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, EXPLAIN_TEXT, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:02.467 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 741106(Integer), 114(Integer), 0(Integer), 201(Integer), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:02.467 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 顶部与承载部形成开放的锅体取放空间(String), 顶部与承载部形成开放的锅体取放空间(String), 741106(Integer), 114(Integer), 0(Integer), 201(Integer), 顶部与承载部形成开放的锅体取放空间(String), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:02.468 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 741107(Integer), 114(Integer), 0(Integer), 201(Integer), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), -1(Integer), 权要2(String), 0(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:02.468 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 741108(Integer), 114(Integer), 0(Integer), 201(Integer), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), -1(Integer), 权要3(String), 0(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:02.468 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 741109(Integer), 114(Integer), 0(Integer), 201(Integer), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), -1(Integer), 权要4(String), 0(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:02.468 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 741110(Integer), 114(Integer), 0(Integer), 201(Integer), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), -1(Integer), 权要5(String), 0(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:02.469 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 741111(Integer), 114(Integer), 0(Integer), 201(Integer), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), -1(Integer), 权要6(String), 0(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:02.469 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 741112(Integer), 114(Integer), 0(Integer), 201(Integer), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), -1(Integer), 权要7(String), 0(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:02.469 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 741113(Integer), 114(Integer), 0(Integer), 201(Integer), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), -1(Integer), 权要8(String), 0(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:02.469 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 741114(Integer), 114(Integer), 0(Integer), 201(Integer), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), -1(Integer), 权要9(String), 0(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:02.470 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 741115(Integer), 114(Integer), 0(Integer), 201(Integer), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), -1(Integer), 权要10(String), 0(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.766 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.767 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.783 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.784 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.784 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.800 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.801 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 201(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.802 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.802 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.802 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.819 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.819 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.821 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.821 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.822 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.822 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.840 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.841 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.841 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.841 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.843 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.844 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体,(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.860 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:03.862 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:04.190 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:04.190 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:04.207 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:04.681 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:04.682 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:04.699 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:04.700 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:04.700 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:04.718 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:04.910 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:04.910 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:04.931 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 79
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:04.932 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:04.932 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:16:04.969 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 9
[rms:0.0.0.0:8885] [,] 2022-12-12 20:18:55.489 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:18:55.489 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:18:55.507 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:18:55.510 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:18:55.510 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:18:55.529 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:18:55.765 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:18:55.765 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:18:55.786 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 70
[rms:0.0.0.0:8885] [,] 2022-12-12 20:18:55.787 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:18:55.787 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:18:55.822 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.189 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.190 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.209 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.209 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.209 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.226 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.235 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.236 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.253 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.253 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.254 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.271 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.275 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.275 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.292 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.293 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.293 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.311 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.500 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.500 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 201(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.520 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 70
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.521 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.521 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 201(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:05.556 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.410 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==>  Preparing: SELECT COUNT(*) AS total FROM REPORT
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.411 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.417 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.417 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.429 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectPage_mpCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.431 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectPage ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT ORDER BY ID DESC LIMIT ?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.431 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectPage ==> Parameters: 10(Long)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.436 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.436 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.436 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.448 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectPage <==      Total: 10
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.449 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,FILE_TYPE,FILE_ID FROM ASSO_REPORT_FILE WHERE (REPORT_ID IN (?,?,?,?,?,?,?,?,?,?))
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.449 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoReportFileMapper.selectList ==> Parameters: 203(Integer), 202(Integer), 201(Integer), 200(Integer), 199(Integer), 198(Integer), 197(Integer), 196(Integer), 195(Integer), 194(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.454 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.456 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.456 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.466 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoReportFileMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.474 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.476 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.477 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.494 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectCount ==>  Preparing: SELECT COUNT( * ) FROM REPORT ORDER BY ID DESC
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.494 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.494 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectCount ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:09.512 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectCount <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.479 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.479 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.497 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.498 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.498 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.515 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.516 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.516 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.532 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.533 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.533 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.551 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.564 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.564 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.582 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.582 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.582 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.600 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.785 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.785 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.803 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 18
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.804 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.804 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 202(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.837 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.838 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.838 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 1.一种框式电饭煲(String), 1.一种框式电饭煲(String), 741106(Integer), 114(Integer), 0(Integer), 202(Integer), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.838 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 包括锅体、框体(String), 包括锅体、框体(String), 741106(Integer), 114(Integer), 0(Integer), 202(Integer), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.838 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 其特征在于(String), 其特征在于(String), 741106(Integer), 114(Integer), 0(Integer), 202(Integer), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.839 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 741106(Integer), 114(Integer), 0(Integer), 202(Integer), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.839 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 顶部与承载部形成开放的锅体取放空间(String), 顶部与承载部形成开放的锅体取放空间(String), 741106(Integer), 114(Integer), 0(Integer), 202(Integer), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.952 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.953 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 741107(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要2(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.989 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.991 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:12.992 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 741108(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.028 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.028 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.028 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 741109(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.064 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.065 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.066 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 741110(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.102 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.103 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.104 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 741111(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.141 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.141 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.141 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 741112(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.177 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.178 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.179 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 741113(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.215 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.215 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.215 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 741114(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.251 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.251 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.251 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 741115(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要10(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:13.287 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:16.258 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:16.258 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 202(Integer), CN109924892B(String), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:16.294 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 14
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:16.294 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, EXPLAIN_TEXT, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:16.295 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 1.一种框式电饭煲(String), 1.一种框式电饭煲(String), 741106(Integer), 114(Integer), 0(Integer), 202(Integer), 1.一种框式电饭煲(String), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:16.296 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 包括锅体、框体(String), 包括锅体、框体(String), 741106(Integer), 114(Integer), 0(Integer), 202(Integer), 包括锅体、框体(String), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:16.297 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 其特征在于(String), 其特征在于(String), 741106(Integer), 114(Integer), 0(Integer), 202(Integer), 其特征在于(String), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:16.297 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 741106(Integer), 114(Integer), 0(Integer), 202(Integer), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:16.298 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 顶部与承载部形成开放的锅体取放空间(String), 顶部与承载部形成开放的锅体取放空间(String), 741106(Integer), 114(Integer), 0(Integer), 202(Integer), 顶部与承载部形成开放的锅体取放空间(String), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:16.298 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, EXPLAIN_TEXT, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:16.299 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 741107(Integer), 114(Integer), 0(Integer), 202(Integer), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), -1(Integer), 权要2(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:16.299 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 741108(Integer), 114(Integer), 0(Integer), 202(Integer), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:16.299 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 741109(Integer), 114(Integer), 0(Integer), 202(Integer), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:16.299 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 741110(Integer), 114(Integer), 0(Integer), 202(Integer), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:16.299 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 741111(Integer), 114(Integer), 0(Integer), 202(Integer), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:16.299 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 741112(Integer), 114(Integer), 0(Integer), 202(Integer), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:16.299 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 741113(Integer), 114(Integer), 0(Integer), 202(Integer), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:16.300 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 741114(Integer), 114(Integer), 0(Integer), 202(Integer), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:16.300 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 741115(Integer), 114(Integer), 0(Integer), 202(Integer), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), -1(Integer), 权要10(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:19.622 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:19.623 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 202(Integer), CN109924892B(String), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:19.659 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 14
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:19.660 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, EXPLAIN_TEXT, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:19.660 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 包括锅体、框体(String), 1.一种框式电饭煲,包括锅体、框体(String), 741106(Integer), 114(Integer), 0(Integer), 202(Integer), 1.一种框式电饭煲,包括锅体、框体(String), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:19.661 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 其特征在于(String), 其特征在于(String), 741106(Integer), 114(Integer), 0(Integer), 202(Integer), 其特征在于(String), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:19.661 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 741106(Integer), 114(Integer), 0(Integer), 202(Integer), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:19.662 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 顶部与承载部形成开放的锅体取放空间(String), 顶部与承载部形成开放的锅体取放空间(String), 741106(Integer), 114(Integer), 0(Integer), 202(Integer), 顶部与承载部形成开放的锅体取放空间(String), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:19.662 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, EXPLAIN_TEXT, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:19.663 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 741107(Integer), 114(Integer), 0(Integer), 202(Integer), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), -1(Integer), 权要2(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:19.664 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 741108(Integer), 114(Integer), 0(Integer), 202(Integer), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:19.664 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 741109(Integer), 114(Integer), 0(Integer), 202(Integer), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:19.665 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 741110(Integer), 114(Integer), 0(Integer), 202(Integer), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:19.665 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 741111(Integer), 114(Integer), 0(Integer), 202(Integer), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:19.666 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 741112(Integer), 114(Integer), 0(Integer), 202(Integer), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:19.666 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 741113(Integer), 114(Integer), 0(Integer), 202(Integer), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:19.667 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 741114(Integer), 114(Integer), 0(Integer), 202(Integer), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:19.667 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 741115(Integer), 114(Integer), 0(Integer), 202(Integer), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), -1(Integer), 权要10(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.400 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.400 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.416 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.416 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.416 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.437 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.437 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 202(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.437 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.437 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.437 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.453 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 13
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.453 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.453 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.453 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.453 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.453 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.468 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.468 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.468 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.468 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.468 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.468 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.484 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.484 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.907 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.907 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:20.922 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:21.178 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:21.178 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:21.209 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:21.209 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:21.209 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:21.225 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:21.402 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:21.402 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:21.418 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 31
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:21.418 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:21.418 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 202(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:21.468 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 9
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:31.091 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:31.091 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 202(Integer), CN109924892B(String), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:31.126 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:31.126 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, EXPLAIN_TEXT, SPLIT_BY, RIGHT_NAME, RIGHT_TYPE, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:31.126 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 包括锅体、框体(String), 1.一种框式电饭煲,包括锅体、框体(String), 741106(Integer), 114(Integer), 0(Integer), 202(Integer), 1.一种框式电饭煲,包括锅体、框体(String), 2(Integer), 权要1(String), 1(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:31.126 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), (String), 、框体(String), 741106(Integer), 114(Integer), 0(Integer), 202(Integer), (String), 2(Integer), 权要1(String), 1(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:31.126 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 其特征在于(String), 其特征在于(String), 741106(Integer), 114(Integer), 0(Integer), 202(Integer), 其特征在于(String), 2(Integer), 权要1(String), 1(Integer), 3(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:31.126 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 741106(Integer), 114(Integer), 0(Integer), 202(Integer), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 2(Integer), 权要1(String), 1(Integer), 4(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:31.127 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 顶部与承载部形成开放的锅体取放空间(String), 顶部与承载部形成开放的锅体取放空间(String), 741106(Integer), 114(Integer), 0(Integer), 202(Integer), 顶部与承载部形成开放的锅体取放空间(String), 2(Integer), 权要1(String), 1(Integer), 5(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:31.127 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 741107(Integer), 114(Integer), 0(Integer), 202(Integer), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), -1(Integer), 权要2(String), 0(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:31.127 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 741108(Integer), 114(Integer), 0(Integer), 202(Integer), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), -1(Integer), 权要3(String), 0(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:31.127 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 741109(Integer), 114(Integer), 0(Integer), 202(Integer), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), -1(Integer), 权要4(String), 0(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:31.127 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 741110(Integer), 114(Integer), 0(Integer), 202(Integer), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), -1(Integer), 权要5(String), 0(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:31.127 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 741111(Integer), 114(Integer), 0(Integer), 202(Integer), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), -1(Integer), 权要6(String), 0(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:31.127 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 741112(Integer), 114(Integer), 0(Integer), 202(Integer), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), -1(Integer), 权要7(String), 0(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:31.127 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 741113(Integer), 114(Integer), 0(Integer), 202(Integer), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), -1(Integer), 权要8(String), 0(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:31.127 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 741114(Integer), 114(Integer), 0(Integer), 202(Integer), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), -1(Integer), 权要9(String), 0(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:31.127 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 741115(Integer), 114(Integer), 0(Integer), 202(Integer), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), -1(Integer), 权要10(String), 0(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.847 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.847 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.865 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.865 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.865 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.882 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.882 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 202(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.883 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.883 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.883 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.901 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.901 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 14
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.902 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.903 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.903 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.903 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.921 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.922 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.922 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.922 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.924 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.924 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.941 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:32.944 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:33.375 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:33.375 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:33.393 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:33.598 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:33.599 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:33.616 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:33.616 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:33.617 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:33.635 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:33.827 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:33.827 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:33.846 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 32
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:33.846 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:33.847 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 202(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:33.884 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 9
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.098 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.099 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.116 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.116 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.116 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.133 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (REPORT_ID = ? AND PARTNER_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.133 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: 202(Integer), 114(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.134 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.135 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.136 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.151 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 5
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.151 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.151 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.154 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.154 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.154 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.169 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.169 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==>  Preparing: select DISTINCT SIGN_PATENT_NO from FEATURES WHERE SIGN_PATENT_NO="0" or CONTENT in ( ? , ? , ? , ? , ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.169 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo ==> Parameters: 1.一种框式电饭煲,包括锅体、框体(String), 、框体(String), 其特征在于(String), 框体包括承载部、由承载部向上延伸形成的支撑部、以及由支撑部向锅体上方延伸的顶部(String), 顶部与承载部形成开放的锅体取放空间(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.172 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.172 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.172 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.187 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.getSignPatentNo <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.189 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.627 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.627 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:53.645 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:58.459 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:58.459 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:58.477 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:58.479 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:58.479 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:58.497 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:58.499 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:58.499 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:58.517 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:58.519 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:58.519 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:58.536 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:58.536 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:58.537 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:58.555 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:58.968 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:58.968 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:58.984 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:59.252 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:59.252 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:59.271 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:59.811 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:59.811 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:59.829 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:59.829 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:59.829 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:59.847 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:59.941 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.insert ==>  Preparing: INSERT INTO COMPARE_FILES ( REPORT_ID, PATENT_NO ) VALUES ( ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:59.942 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.insert ==> Parameters: 202(Integer), CN109924892B(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:59.942 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.insert ==> Parameters: 202(Integer), JP1994296558A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:59.942 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.insert ==> Parameters: 202(Integer), JP2003093227A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:59.942 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.insert ==> Parameters: 202(Integer), CN102727071A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:59.942 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.insert ==> Parameters: 202(Integer), CN201312722Y(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:59.942 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.insert ==> Parameters: 202(Integer), CN2258371Y(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:59.942 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.insert ==> Parameters: 202(Integer), KR1020160016352A(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:19:59.942 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.insert ==> Parameters: 202(Integer), US20110256287A1(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:00.150 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:00.151 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:00.168 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:00.168 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:00.168 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:00.186 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:00.187 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:00.188 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:00.205 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:00.207 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:00.208 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:00.226 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:00.226 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:00.227 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:00.245 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:00.525 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:00.525 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:00.543 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:06.543 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:06.543 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:06.561 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.116 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.116 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.134 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.134 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.134 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.152 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.221 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.221 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.239 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.240 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.240 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.256 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.257 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.257 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.274 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.274 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.274 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.292 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.292 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.292 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.310 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.592 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.592 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:07.610 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:17.331 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:17.331 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:17.349 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:17.908 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:17.908 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:17.926 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:17.926 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:17.926 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:17.944 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:18.000 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:18.000 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:18.023 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:18.023 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:18.024 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:18.041 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:18.041 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT SIGN_PATENT_NO FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:18.041 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:18.059 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:18.059 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:18.059 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:18.077 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:18.078 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:18.078 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:18.097 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:18.402 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==>  Preparing: select count(*) from COMPARE_FILES where REPORT_ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:18.402 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:18.420 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectedTotal <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:23.623 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:23.624 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 202(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:23.642 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:23.643 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:23.644 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:23.662 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:23.664 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:23.665 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:23.682 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:23.683 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:23.683 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:23.702 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:41.188 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:41.189 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 202(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:41.206 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:41.207 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:41.207 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:41.225 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:41.225 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:41.225 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:41.243 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:41.243 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:41.243 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:41.261 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:56.018 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:56.019 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:56.037 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:56.038 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.updateById ==>  Preparing: UPDATE REPORT SET SIGN_PATENT_NO=?, NAME=?, PRO_TEC=?, TYPE=?, STATUS=?, CREATE_TIME=?, PERSON_ID=?, PERSON_NAME=?, CLIENT_ID=?, CLIENT_NAME=?, DEPARTMENT_ID=?, DEPARTMENT_NAME=?, SCENARIO_ID=?, PROJECT_ID=?, SPLIT_BY=?, SPLIT_TYPE=?, CREATE_PERSON_ID=?, CREATE_PERSON_NAME=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:56.038 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.updateById ==> Parameters: CN109924892B(String), CN109924892B无效分析(String), (String), 0(Integer), 2(Integer), 2022-12-12 20:12:59.0(Timestamp), 3(Integer), 大华管理员(String), 61(Integer), 陈宇(String), 53(Integer), 测试部门syy(String), 1(String), 179(Integer), 2(Integer), 0(Integer), 103(Integer), 沈永艺(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:56.074 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:56.182 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT PATENT_NO FROM COMPARE_FILES WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:56.182 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:20:56.200 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.729 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.729 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.747 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.747 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.747 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.758 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.758 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 202(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.765 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.765 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.765 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.777 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.777 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.777 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.782 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.782 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.782 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.795 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.795 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.795 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.800 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.812 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.812 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.812 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.815 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.815 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.830 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.835 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.835 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.835 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:07.855 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.069 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.069 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.085 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 23
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.085 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.085 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 202(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.116 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.116 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.116 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 741107(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要2(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.168 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.168 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.168 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 741108(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.200 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.200 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.200 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 741109(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.246 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.246 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.246 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 741110(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.278 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.278 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.278 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 741111(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.325 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.325 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.325 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 741112(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.356 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.356 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.356 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 741113(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.408 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.408 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.408 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 741114(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.440 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.440 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.440 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 741115(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要10(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:08.486 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:20.538 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:20.538 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 202(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:20.558 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:20.558 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:20.558 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:20.577 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:20.577 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:20.577 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:20.597 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:20.597 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:20.597 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:22:20.616 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:23:10.746 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:23:10.747 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:23:10.767 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:23:10.767 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.updateById ==>  Preparing: UPDATE REPORT SET SIGN_PATENT_NO=?, NAME=?, PRO_TEC=?, TYPE=?, STATUS=?, CREATE_TIME=?, PERSON_ID=?, PERSON_NAME=?, CLIENT_ID=?, CLIENT_NAME=?, DEPARTMENT_ID=?, DEPARTMENT_NAME=?, SCENARIO_ID=?, PROJECT_ID=?, SPLIT_BY=?, SPLIT_TYPE=?, CREATE_PERSON_ID=?, CREATE_PERSON_NAME=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:23:10.768 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.updateById ==> Parameters: CN109924892B(String), CN109924892B无效分析(String), (String), 0(Integer), 2(Integer), 2022-12-12 20:12:59.0(Timestamp), 3(Integer), 大华管理员(String), 61(Integer), 陈宇(String), 53(Integer), 测试部门syy(String), 1(String), 179(Integer), 2(Integer), 0(Integer), 103(Integer), 沈永艺(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:23:10.807 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:23:10.923 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT PATENT_NO FROM COMPARE_FILES WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:23:10.923 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:23:10.942 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:23:23.669 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:23:23.669 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:23:23.689 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:23:23.690 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.updateById ==>  Preparing: UPDATE REPORT SET SIGN_PATENT_NO=?, NAME=?, PRO_TEC=?, TYPE=?, STATUS=?, CREATE_TIME=?, PERSON_ID=?, PERSON_NAME=?, CLIENT_ID=?, CLIENT_NAME=?, DEPARTMENT_ID=?, DEPARTMENT_NAME=?, SCENARIO_ID=?, PROJECT_ID=?, SPLIT_BY=?, SPLIT_TYPE=?, CREATE_PERSON_ID=?, CREATE_PERSON_NAME=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:23:23.690 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.updateById ==> Parameters: CN109924892B(String), CN109924892B无效分析(String), (String), 0(Integer), 2(Integer), 2022-12-12 20:12:59.0(Timestamp), 3(Integer), 大华管理员(String), 61(Integer), 陈宇(String), 53(Integer), 测试部门syy(String), 1(String), 179(Integer), 2(Integer), 0(Integer), 103(Integer), 沈永艺(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:23:23.729 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:23:23.844 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT PATENT_NO FROM COMPARE_FILES WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:23:23.844 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:23:23.863 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:12.725 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:12.726 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:12.747 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:12.748 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.updateById ==>  Preparing: UPDATE REPORT SET SIGN_PATENT_NO=?, NAME=?, PRO_TEC=?, TYPE=?, STATUS=?, CREATE_TIME=?, PERSON_ID=?, PERSON_NAME=?, CLIENT_ID=?, CLIENT_NAME=?, DEPARTMENT_ID=?, DEPARTMENT_NAME=?, SCENARIO_ID=?, PROJECT_ID=?, SPLIT_BY=?, SPLIT_TYPE=?, CREATE_PERSON_ID=?, CREATE_PERSON_NAME=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:12.751 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.updateById ==> Parameters: CN109924892B(String), CN109924892B无效分析(String), (String), 0(Integer), 2(Integer), 2022-12-12 20:12:59.0(Timestamp), 3(Integer), 大华管理员(String), 61(Integer), 陈宇(String), 53(Integer), 测试部门syy(String), 1(String), 179(Integer), 2(Integer), 0(Integer), 103(Integer), 沈永艺(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:12.789 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:12.899 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT PATENT_NO FROM COMPARE_FILES WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:12.900 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:12.919 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:22.900 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:22.900 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:22.931 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:22.931 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.updateById ==>  Preparing: UPDATE REPORT SET SIGN_PATENT_NO=?, NAME=?, PRO_TEC=?, TYPE=?, STATUS=?, CREATE_TIME=?, PERSON_ID=?, PERSON_NAME=?, CLIENT_ID=?, CLIENT_NAME=?, DEPARTMENT_ID=?, DEPARTMENT_NAME=?, SCENARIO_ID=?, PROJECT_ID=?, SPLIT_BY=?, SPLIT_TYPE=?, CREATE_PERSON_ID=?, CREATE_PERSON_NAME=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:22.931 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.updateById ==> Parameters: CN109924892B(String), CN109924892B无效分析(String), (String), 0(Integer), 2(Integer), 2022-12-12 20:12:59.0(Timestamp), 3(Integer), 大华管理员(String), 61(Integer), 陈宇(String), 53(Integer), 测试部门syy(String), 1(String), 179(Integer), 2(Integer), 0(Integer), 103(Integer), 沈永艺(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:22.962 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:23.078 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT PATENT_NO FROM COMPARE_FILES WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:23.078 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:23.097 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:33.770 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:33.770 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:33.802 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:33.802 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.updateById ==>  Preparing: UPDATE REPORT SET SIGN_PATENT_NO=?, NAME=?, PRO_TEC=?, TYPE=?, STATUS=?, CREATE_TIME=?, PERSON_ID=?, PERSON_NAME=?, CLIENT_ID=?, CLIENT_NAME=?, DEPARTMENT_ID=?, DEPARTMENT_NAME=?, SCENARIO_ID=?, PROJECT_ID=?, SPLIT_BY=?, SPLIT_TYPE=?, CREATE_PERSON_ID=?, CREATE_PERSON_NAME=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:33.802 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.updateById ==> Parameters: CN109924892B(String), CN109924892B无效分析(String), (String), 0(Integer), 2(Integer), 2022-12-12 20:12:59.0(Timestamp), 3(Integer), 大华管理员(String), 61(Integer), 陈宇(String), 53(Integer), 测试部门syy(String), 1(String), 179(Integer), 2(Integer), 0(Integer), 103(Integer), 沈永艺(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:33.837 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:33.953 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT PATENT_NO FROM COMPARE_FILES WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:33.953 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:33.969 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:41.516 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:41.516 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:41.535 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:41.536 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.updateById ==>  Preparing: UPDATE REPORT SET SIGN_PATENT_NO=?, NAME=?, PRO_TEC=?, TYPE=?, STATUS=?, CREATE_TIME=?, PERSON_ID=?, PERSON_NAME=?, CLIENT_ID=?, CLIENT_NAME=?, DEPARTMENT_ID=?, DEPARTMENT_NAME=?, SCENARIO_ID=?, PROJECT_ID=?, SPLIT_BY=?, SPLIT_TYPE=?, CREATE_PERSON_ID=?, CREATE_PERSON_NAME=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:41.537 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.updateById ==> Parameters: CN109924892B(String), CN109924892B无效分析(String), (String), 0(Integer), 2(Integer), 2022-12-12 20:12:59.0(Timestamp), 3(Integer), 大华管理员(String), 61(Integer), 陈宇(String), 53(Integer), 测试部门syy(String), 1(String), 179(Integer), 2(Integer), 0(Integer), 103(Integer), 沈永艺(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:41.576 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.ReportMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:41.687 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT PATENT_NO FROM COMPARE_FILES WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:41.687 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:41.706 DEBUG 5496 [http-nio-8885-exec-7] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:51.895 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:51.895 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:51.914 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:51.915 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.updateById ==>  Preparing: UPDATE REPORT SET SIGN_PATENT_NO=?, NAME=?, PRO_TEC=?, TYPE=?, STATUS=?, CREATE_TIME=?, PERSON_ID=?, PERSON_NAME=?, CLIENT_ID=?, CLIENT_NAME=?, DEPARTMENT_ID=?, DEPARTMENT_NAME=?, SCENARIO_ID=?, PROJECT_ID=?, SPLIT_BY=?, SPLIT_TYPE=?, CREATE_PERSON_ID=?, CREATE_PERSON_NAME=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:51.916 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.updateById ==> Parameters: CN109924892B(String), CN109924892B无效分析(String), (String), 0(Integer), 2(Integer), 2022-12-12 20:12:59.0(Timestamp), 3(Integer), 大华管理员(String), 61(Integer), 陈宇(String), 53(Integer), 测试部门syy(String), 1(String), 179(Integer), 2(Integer), 0(Integer), 103(Integer), 沈永艺(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:51.955 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.ReportMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:52.064 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT PATENT_NO FROM COMPARE_FILES WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:52.064 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:24:52.079 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:04.940 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:04.940 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:04.971 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:04.971 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.updateById ==>  Preparing: UPDATE REPORT SET SIGN_PATENT_NO=?, NAME=?, PRO_TEC=?, TYPE=?, STATUS=?, CREATE_TIME=?, PERSON_ID=?, PERSON_NAME=?, CLIENT_ID=?, CLIENT_NAME=?, DEPARTMENT_ID=?, DEPARTMENT_NAME=?, SCENARIO_ID=?, PROJECT_ID=?, SPLIT_BY=?, SPLIT_TYPE=?, CREATE_PERSON_ID=?, CREATE_PERSON_NAME=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:04.971 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.updateById ==> Parameters: CN109924892B(String), CN109924892B无效分析(String), (String), 0(Integer), 2(Integer), 2022-12-12 20:12:59.0(Timestamp), 3(Integer), 大华管理员(String), 61(Integer), 陈宇(String), 53(Integer), 测试部门syy(String), 1(String), 179(Integer), 2(Integer), 0(Integer), 103(Integer), 沈永艺(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:05.012 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:05.115 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT PATENT_NO FROM COMPARE_FILES WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:05.116 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:05.134 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:24.968 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:24.969 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:24.989 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:24.990 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.updateById ==>  Preparing: UPDATE REPORT SET SIGN_PATENT_NO=?, NAME=?, PRO_TEC=?, TYPE=?, STATUS=?, CREATE_TIME=?, PERSON_ID=?, PERSON_NAME=?, CLIENT_ID=?, CLIENT_NAME=?, DEPARTMENT_ID=?, DEPARTMENT_NAME=?, SCENARIO_ID=?, PROJECT_ID=?, SPLIT_BY=?, SPLIT_TYPE=?, CREATE_PERSON_ID=?, CREATE_PERSON_NAME=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:24.990 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.updateById ==> Parameters: CN109924892B(String), CN109924892B无效分析(String), (String), 0(Integer), 2(Integer), 2022-12-12 20:12:59.0(Timestamp), 3(Integer), 大华管理员(String), 61(Integer), 陈宇(String), 53(Integer), 测试部门syy(String), 1(String), 179(Integer), 2(Integer), 0(Integer), 103(Integer), 沈永艺(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:25.022 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:25.131 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT PATENT_NO FROM COMPARE_FILES WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:25.131 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:25.162 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.833 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.833 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.852 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.855 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.855 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.874 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.874 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 202(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.874 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.876 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.876 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.895 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.895 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.895 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.897 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.898 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.898 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.914 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.915 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.915 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.915 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.917 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.917 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.932 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.932 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.932 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.936 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.936 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.936 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.950 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:30.956 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:31.164 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:31.164 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:31.185 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 32
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:31.185 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:31.186 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 202(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:31.226 DEBUG 5496 [http-nio-8885-exec-8] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 9
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:43.684 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:43.684 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 202(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:43.707 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:43.707 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:43.707 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:43.722 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:43.738 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:43.738 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:43.754 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:43.754 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:43.754 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:43.769 DEBUG 5496 [http-nio-8885-exec-2] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:55.110 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:55.110 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:55.125 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:55.125 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.updateById ==>  Preparing: UPDATE REPORT SET SIGN_PATENT_NO=?, NAME=?, PRO_TEC=?, TYPE=?, STATUS=?, CREATE_TIME=?, PERSON_ID=?, PERSON_NAME=?, CLIENT_ID=?, CLIENT_NAME=?, DEPARTMENT_ID=?, DEPARTMENT_NAME=?, SCENARIO_ID=?, PROJECT_ID=?, SPLIT_BY=?, SPLIT_TYPE=?, CREATE_PERSON_ID=?, CREATE_PERSON_NAME=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:55.125 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.updateById ==> Parameters: CN109924892B(String), CN109924892B无效分析(String), (String), 0(Integer), 2(Integer), 2022-12-12 20:12:59.0(Timestamp), 3(Integer), 大华管理员(String), 61(Integer), 陈宇(String), 53(Integer), 测试部门syy(String), 1(String), 179(Integer), 2(Integer), 0(Integer), 103(Integer), 沈永艺(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:55.157 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.ReportMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:55.271 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT PATENT_NO FROM COMPARE_FILES WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:55.271 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:25:55.302 DEBUG 5496 [http-nio-8885-exec-9] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:22.856 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:22.856 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:22.871 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:22.871 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.updateById ==>  Preparing: UPDATE REPORT SET SIGN_PATENT_NO=?, NAME=?, PRO_TEC=?, TYPE=?, STATUS=?, CREATE_TIME=?, PERSON_ID=?, PERSON_NAME=?, CLIENT_ID=?, CLIENT_NAME=?, DEPARTMENT_ID=?, DEPARTMENT_NAME=?, SCENARIO_ID=?, PROJECT_ID=?, SPLIT_BY=?, SPLIT_TYPE=?, CREATE_PERSON_ID=?, CREATE_PERSON_NAME=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:22.871 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.updateById ==> Parameters: CN109924892B(String), CN109924892B无效分析(String), (String), 0(Integer), 2(Integer), 2022-12-12 20:12:59.0(Timestamp), 3(Integer), 大华管理员(String), 61(Integer), 陈宇(String), 53(Integer), 测试部门syy(String), 1(String), 179(Integer), 2(Integer), 0(Integer), 103(Integer), 沈永艺(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:22.908 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.ReportMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:23.029 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT PATENT_NO FROM COMPARE_FILES WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:23.029 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:23.048 DEBUG 5496 [http-nio-8885-exec-10] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:32.286 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:32.286 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:32.302 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:32.302 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.updateById ==>  Preparing: UPDATE REPORT SET SIGN_PATENT_NO=?, NAME=?, PRO_TEC=?, TYPE=?, STATUS=?, CREATE_TIME=?, PERSON_ID=?, PERSON_NAME=?, CLIENT_ID=?, CLIENT_NAME=?, DEPARTMENT_ID=?, DEPARTMENT_NAME=?, SCENARIO_ID=?, PROJECT_ID=?, SPLIT_BY=?, SPLIT_TYPE=?, CREATE_PERSON_ID=?, CREATE_PERSON_NAME=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:32.302 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.updateById ==> Parameters: CN109924892B(String), CN109924892B无效分析(String), (String), 0(Integer), 2(Integer), 2022-12-12 20:12:59.0(Timestamp), 3(Integer), 大华管理员(String), 61(Integer), 陈宇(String), 53(Integer), 测试部门syy(String), 1(String), 179(Integer), 2(Integer), 0(Integer), 103(Integer), 沈永艺(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:32.337 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:32.438 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT PATENT_NO FROM COMPARE_FILES WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:32.438 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:32.469 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.811 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.812 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: 
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.831 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 17
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.831 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.831 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_STATE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.850 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 6
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.850 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.850 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: REPORT_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.852 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.852 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 202(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.869 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.869 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 7
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.869 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.869 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==>  Preparing: SELECT ID,DICT_PARENT_KEY,DICT_CHILD_LABEL,DICT_CHILD_VALUE FROM SYS_DICT_ITEM WHERE (DICT_PARENT_KEY = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.869 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.869 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList ==> Parameters: TASK_TYPE(String)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.887 DEBUG 5496 [http-nio-8885-exec-5] cn.cslg.report.mapper.SystemDictItemMapper.selectList <==      Total: 4
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.889 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.889 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.889 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.895 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.895 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.908 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.908 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.908 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.912 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.912 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.912 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.927 DEBUG 5496 [http-nio-8885-exec-3] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:37.931 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.137 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,CONTENT_OUT,CONTENT,RIGHT_ID,PARTNER_ID,IS_FINAL,REPORT_ID,EXPLAIN_TEXT,SPLIT_BY,RIGHT_NAME,RIGHT_TYPE,FEATURES_ORDER FROM FEATURES WHERE (SIGN_PATENT_NO = ? AND REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.137 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList ==> Parameters: CN109924892B(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.155 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.selectList <==      Total: 23
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.155 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==>  Preparing: DELETE FROM FEATURES WHERE (REPORT_ID = ? AND SIGN_PATENT_NO = ? AND PARTNER_ID = ? AND SPLIT_BY <> ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.155 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete ==> Parameters: 202(Integer), CN109924892B(String), 114(Integer), 2(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.191 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.delete <==    Updates: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.192 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.192 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 2.如权利要求1所述的一种框式电饭煲，其特征在于，在水平向所述支撑部位于所述锅体取放空间的任意一侧，锅体取放空间的其余区域均与外部环境连通(String), 741107(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要2(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.228 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.229 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.230 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 3.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部与所述顶部平行设置，且所述承载部与所述顶部之间的纵向间距大于等于所述锅体的高度(String), 741108(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要3(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.267 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.267 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.267 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 4.如权利要求3所述的一种框式电饭煲，其特征在于，所述支撑部垂直于所述承载部，所述支撑部与所述承载部连接处临近所述承载部的中心区域(String), 741109(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要4(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.303 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.304 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.305 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 5.如权利要求1所述的一种框式电饭煲，其特征在于，所述支撑部由所述支撑挡板构成(String), 741110(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要5(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.341 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.342 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.342 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 6.如权利要求1所述的一种框式电饭煲，其特征在于，所述承载部、支撑部以及顶部一体成型(String), 741111(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要6(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.378 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.379 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.380 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 7.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述顶部放置蒸汽发生器，烹饪过程中，所述蒸汽发生器将蒸汽导入所述锅体中进行烹饪(String), 741112(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要7(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.416 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.417 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.418 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 8.如权利要求7所述的一种框式电饭煲，其特征在于，所述框式电饭煲还包括与蒸汽发生器连接的水箱，所述水箱固定于所述框式电饭煲上或所述水箱单独设置且通过水管与所述蒸汽发生器连接(String), 741113(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要8(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.455 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.455 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.455 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 9.如权利要求1-6之一所述的一种框式电饭煲，其特征在于，所述承载部处还设置有加热装置，所述加热装置为加热盘或IH电磁线盘(String), 741114(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要9(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.491 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.491 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==>  Preparing: INSERT INTO FEATURES ( SIGN_PATENT_NO, CONTENT_OUT, CONTENT, RIGHT_ID, PARTNER_ID, IS_FINAL, REPORT_ID, SPLIT_BY, RIGHT_NAME, FEATURES_ORDER ) VALUES ( ?, ?, ?, ?, ?, ?, ?, ?, ?, ? )
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.491 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert ==> Parameters: CN109924892B(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 10.如权利要求7所述的一种框式电饭煲，其特征在于，所述锅体采用保温锅体(String), 741115(Integer), 114(Integer), 0(Integer), 202(Integer), -1(Integer), 权要10(String), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:38.528 DEBUG 5496 [http-nio-8885-exec-4] cn.cslg.report.mapper.FeatureMapper.insert <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:49.386 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==>  Preparing: SELECT ID,TASK_ID,TASK_TYPE,PERSON_ID AS personelId,PERSON_TYPE AS personelType,REPORT_ID,PATENT_NO,STATE FROM ASSO_TASK_PERSONEL WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:49.386 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList ==> Parameters: 202(Integer), 1(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:49.417 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.AssoTaskPersonelMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:49.417 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT ID,REPORT_ID,PATENT_NO,REMARK,STATE FROM COMPARE_FILES WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:49.417 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:49.437 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:49.437 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==>  Preparing: SELECT ID,TASK_NAME,REPORT_ID,IMPORT_COUNT,CREATE_DATE,FINISH_TIME,CREATE_USER_ID,CREATE_USER_NAME,FILE_PATH,STATE,TYPE AS importType FROM IMPORT_TASK WHERE (REPORT_ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:49.437 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:49.453 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ImportTaskMapper.selectList <==      Total: 0
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:49.453 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:49.453 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:26:49.469 DEBUG 5496 [http-nio-8885-exec-6] cn.cslg.report.mapper.ReportMapper.selectById <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:27:00.330 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==>  Preparing: SELECT ID,SIGN_PATENT_NO,NAME,PRO_TEC,TYPE,STATUS,CREATE_TIME,REPORT_FILE_ID,PERSON_ID,PERSON_NAME,CLIENT_ID,CLIENT_NAME,DEPARTMENT_ID,DEPARTMENT_NAME,ASSOCIATE_REPORT_ID,ASSOCIATE_REPORT_NAME,SCENARIO_ID,IT_FLAG,PROJECT_ID,VOLUME_NUMBER,SPLIT_BY,SPLIT_TYPE,CREATE_PERSON_ID,CREATE_PERSON_NAME FROM REPORT WHERE (ID = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:27:00.330 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList ==> Parameters: 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:27:00.349 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.selectList <==      Total: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:27:00.349 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.updateById ==>  Preparing: UPDATE REPORT SET SIGN_PATENT_NO=?, NAME=?, PRO_TEC=?, TYPE=?, STATUS=?, CREATE_TIME=?, PERSON_ID=?, PERSON_NAME=?, CLIENT_ID=?, CLIENT_NAME=?, DEPARTMENT_ID=?, DEPARTMENT_NAME=?, SCENARIO_ID=?, PROJECT_ID=?, SPLIT_BY=?, SPLIT_TYPE=?, CREATE_PERSON_ID=?, CREATE_PERSON_NAME=? WHERE ID=?
[rms:0.0.0.0:8885] [,] 2022-12-12 20:27:00.349 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.updateById ==> Parameters: CN109924892B(String), CN109924892B无效分析(String), (String), 0(Integer), 2(Integer), 2022-12-12 20:12:59.0(Timestamp), 3(Integer), 大华管理员(String), 61(Integer), 陈宇(String), 53(Integer), 测试部门syy(String), 1(String), 179(Integer), 2(Integer), 0(Integer), 103(Integer), 沈永艺(String), 202(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:27:00.383 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.ReportMapper.updateById <==    Updates: 1
[rms:0.0.0.0:8885] [,] 2022-12-12 20:27:00.491 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==>  Preparing: SELECT PATENT_NO FROM COMPARE_FILES WHERE (REPORT_ID = ? AND STATE = ?)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:27:00.491 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList ==> Parameters: 202(Integer), 0(Integer)
[rms:0.0.0.0:8885] [,] 2022-12-12 20:27:00.509 DEBUG 5496 [http-nio-8885-exec-1] cn.cslg.report.mapper.CompareFilesMapper.selectList <==      Total: 8